mux.h 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261
  1. /*
  2. * mux.h
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #ifndef _MUX_H_
  16. #define _MUX_H_
  17. #include <common.h>
  18. #include <asm/io.h>
  19. #define MUX_CFG(value, offset) \
  20. __raw_writel(value, (CTRL_BASE + offset));
  21. /* PAD Control Fields */
  22. #define SLEWCTRL (0x1 << 6)
  23. #define RXACTIVE (0x1 << 5)
  24. #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
  25. #define PULLUDEN (0x0 << 3) /* Pull up enabled */
  26. #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
  27. #define MODE(val) val /* used for Readability */
  28. /*
  29. * PAD CONTROL OFFSETS
  30. * Field names corresponds to the pad signal name
  31. */
  32. struct pad_signals {
  33. int gpmc_ad0;
  34. int gpmc_ad1;
  35. int gpmc_ad2;
  36. int gpmc_ad3;
  37. int gpmc_ad4;
  38. int gpmc_ad5;
  39. int gpmc_ad6;
  40. int gpmc_ad7;
  41. int gpmc_ad8;
  42. int gpmc_ad9;
  43. int gpmc_ad10;
  44. int gpmc_ad11;
  45. int gpmc_ad12;
  46. int gpmc_ad13;
  47. int gpmc_ad14;
  48. int gpmc_ad15;
  49. int gpmc_a0;
  50. int gpmc_a1;
  51. int gpmc_a2;
  52. int gpmc_a3;
  53. int gpmc_a4;
  54. int gpmc_a5;
  55. int gpmc_a6;
  56. int gpmc_a7;
  57. int gpmc_a8;
  58. int gpmc_a9;
  59. int gpmc_a10;
  60. int gpmc_a11;
  61. int gpmc_wait0;
  62. int gpmc_wpn;
  63. int gpmc_be1n;
  64. int gpmc_csn0;
  65. int gpmc_csn1;
  66. int gpmc_csn2;
  67. int gpmc_csn3;
  68. int gpmc_clk;
  69. int gpmc_advn_ale;
  70. int gpmc_oen_ren;
  71. int gpmc_wen;
  72. int gpmc_be0n_cle;
  73. int lcd_data0;
  74. int lcd_data1;
  75. int lcd_data2;
  76. int lcd_data3;
  77. int lcd_data4;
  78. int lcd_data5;
  79. int lcd_data6;
  80. int lcd_data7;
  81. int lcd_data8;
  82. int lcd_data9;
  83. int lcd_data10;
  84. int lcd_data11;
  85. int lcd_data12;
  86. int lcd_data13;
  87. int lcd_data14;
  88. int lcd_data15;
  89. int lcd_vsync;
  90. int lcd_hsync;
  91. int lcd_pclk;
  92. int lcd_ac_bias_en;
  93. int mmc0_dat3;
  94. int mmc0_dat2;
  95. int mmc0_dat1;
  96. int mmc0_dat0;
  97. int mmc0_clk;
  98. int mmc0_cmd;
  99. int mii1_col;
  100. int mii1_crs;
  101. int mii1_rxerr;
  102. int mii1_txen;
  103. int mii1_rxdv;
  104. int mii1_txd3;
  105. int mii1_txd2;
  106. int mii1_txd1;
  107. int mii1_txd0;
  108. int mii1_txclk;
  109. int mii1_rxclk;
  110. int mii1_rxd3;
  111. int mii1_rxd2;
  112. int mii1_rxd1;
  113. int mii1_rxd0;
  114. int rmii1_refclk;
  115. int mdio_data;
  116. int mdio_clk;
  117. int spi0_sclk;
  118. int spi0_d0;
  119. int spi0_d1;
  120. int spi0_cs0;
  121. int spi0_cs1;
  122. int ecap0_in_pwm0_out;
  123. int uart0_ctsn;
  124. int uart0_rtsn;
  125. int uart0_rxd;
  126. int uart0_txd;
  127. int uart1_ctsn;
  128. int uart1_rtsn;
  129. int uart1_rxd;
  130. int uart1_txd;
  131. int i2c0_sda;
  132. int i2c0_scl;
  133. int mcasp0_aclkx;
  134. int mcasp0_fsx;
  135. int mcasp0_axr0;
  136. int mcasp0_ahclkr;
  137. int mcasp0_aclkr;
  138. int mcasp0_fsr;
  139. int mcasp0_axr1;
  140. int mcasp0_ahclkx;
  141. int xdma_event_intr0;
  142. int xdma_event_intr1;
  143. int nresetin_out;
  144. int porz;
  145. int nnmi;
  146. int osc0_in;
  147. int osc0_out;
  148. int rsvd1;
  149. int tms;
  150. int tdi;
  151. int tdo;
  152. int tck;
  153. int ntrst;
  154. int emu0;
  155. int emu1;
  156. int osc1_in;
  157. int osc1_out;
  158. int pmic_power_en;
  159. int rtc_porz;
  160. int rsvd2;
  161. int ext_wakeup;
  162. int enz_kaldo_1p8v;
  163. int usb0_dm;
  164. int usb0_dp;
  165. int usb0_ce;
  166. int usb0_id;
  167. int usb0_vbus;
  168. int usb0_drvvbus;
  169. int usb1_dm;
  170. int usb1_dp;
  171. int usb1_ce;
  172. int usb1_id;
  173. int usb1_vbus;
  174. int usb1_drvvbus;
  175. int ddr_resetn;
  176. int ddr_csn0;
  177. int ddr_cke;
  178. int ddr_ck;
  179. int ddr_nck;
  180. int ddr_casn;
  181. int ddr_rasn;
  182. int ddr_wen;
  183. int ddr_ba0;
  184. int ddr_ba1;
  185. int ddr_ba2;
  186. int ddr_a0;
  187. int ddr_a1;
  188. int ddr_a2;
  189. int ddr_a3;
  190. int ddr_a4;
  191. int ddr_a5;
  192. int ddr_a6;
  193. int ddr_a7;
  194. int ddr_a8;
  195. int ddr_a9;
  196. int ddr_a10;
  197. int ddr_a11;
  198. int ddr_a12;
  199. int ddr_a13;
  200. int ddr_a14;
  201. int ddr_a15;
  202. int ddr_odt;
  203. int ddr_d0;
  204. int ddr_d1;
  205. int ddr_d2;
  206. int ddr_d3;
  207. int ddr_d4;
  208. int ddr_d5;
  209. int ddr_d6;
  210. int ddr_d7;
  211. int ddr_d8;
  212. int ddr_d9;
  213. int ddr_d10;
  214. int ddr_d11;
  215. int ddr_d12;
  216. int ddr_d13;
  217. int ddr_d14;
  218. int ddr_d15;
  219. int ddr_dqm0;
  220. int ddr_dqm1;
  221. int ddr_dqs0;
  222. int ddr_dqsn0;
  223. int ddr_dqs1;
  224. int ddr_dqsn1;
  225. int ddr_vref;
  226. int ddr_vtp;
  227. int ddr_strben0;
  228. int ddr_strben1;
  229. int ain7;
  230. int ain6;
  231. int ain5;
  232. int ain4;
  233. int ain3;
  234. int ain2;
  235. int ain1;
  236. int ain0;
  237. int vrefp;
  238. int vrefn;
  239. };
  240. struct module_pin_mux {
  241. short reg_offset;
  242. unsigned char val;
  243. };
  244. /* Pad control register offset */
  245. #define PAD_CTRL_BASE 0x800
  246. #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
  247. (PAD_CTRL_BASE))->x)
  248. /*
  249. * Configure the pin mux for the module
  250. */
  251. void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
  252. #endif