mem.c 8.0 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Author :
  6. * Manikandan Pillai <mani.pillai@ti.com>
  7. *
  8. * Initial Code from:
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <khasim@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <asm/io.h>
  29. #include <asm/arch/mem.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <command.h>
  32. /*
  33. * Only One NAND allowed on board at a time.
  34. * The GPMC CS Base for the same
  35. */
  36. unsigned int boot_flash_base;
  37. unsigned int boot_flash_off;
  38. unsigned int boot_flash_sec;
  39. unsigned int boot_flash_type;
  40. volatile unsigned int boot_flash_env_addr;
  41. struct gpmc *gpmc_cfg;
  42. #if defined(CONFIG_CMD_NAND)
  43. static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
  44. M_NAND_GPMC_CONFIG1,
  45. M_NAND_GPMC_CONFIG2,
  46. M_NAND_GPMC_CONFIG3,
  47. M_NAND_GPMC_CONFIG4,
  48. M_NAND_GPMC_CONFIG5,
  49. M_NAND_GPMC_CONFIG6, 0
  50. };
  51. #if defined(CONFIG_ENV_IS_IN_NAND)
  52. #define GPMC_CS 0
  53. #else
  54. #define GPMC_CS 1
  55. #endif
  56. #endif
  57. #if defined(CONFIG_CMD_ONENAND)
  58. static const u32 gpmc_onenand[GPMC_MAX_REG] = {
  59. ONENAND_GPMC_CONFIG1,
  60. ONENAND_GPMC_CONFIG2,
  61. ONENAND_GPMC_CONFIG3,
  62. ONENAND_GPMC_CONFIG4,
  63. ONENAND_GPMC_CONFIG5,
  64. ONENAND_GPMC_CONFIG6, 0
  65. };
  66. #if defined(CONFIG_ENV_IS_IN_ONENAND)
  67. #define GPMC_CS 0
  68. #else
  69. #define GPMC_CS 1
  70. #endif
  71. #endif
  72. static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
  73. /**************************************************************************
  74. * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
  75. * command line mem=xyz use all memory with out discontinuous support
  76. * compiled in. Could do it at the ATAG, but there really is two banks...
  77. * Called as part of 2nd phase DDR init.
  78. **************************************************************************/
  79. void make_cs1_contiguous(void)
  80. {
  81. u32 size, a_add_low, a_add_high;
  82. size = get_sdr_cs_size(CS0);
  83. size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
  84. a_add_high = (size & 3) << 8; /* set up low field */
  85. a_add_low = (size & 0x3C) >> 2; /* set up high field */
  86. writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
  87. }
  88. /********************************************************
  89. * mem_ok() - test used to see if timings are correct
  90. * for a part. Helps in guessing which part
  91. * we are currently using.
  92. *******************************************************/
  93. u32 mem_ok(u32 cs)
  94. {
  95. u32 val1, val2, addr;
  96. u32 pattern = 0x12345678;
  97. addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  98. writel(0x0, addr + 0x400); /* clear pos A */
  99. writel(pattern, addr); /* pattern to pos B */
  100. writel(0x0, addr + 4); /* remove pattern off the bus */
  101. val1 = readl(addr + 0x400); /* get pos A value */
  102. val2 = readl(addr); /* get val2 */
  103. if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
  104. return 0;
  105. else
  106. return 1;
  107. }
  108. /********************************************************
  109. * sdrc_init() - init the sdrc chip selects CS0 and CS1
  110. * - early init routines, called from flash or
  111. * SRAM.
  112. *******************************************************/
  113. void sdrc_init(void)
  114. {
  115. /* only init up first bank here */
  116. do_sdrc_init(CS0, EARLY_INIT);
  117. }
  118. /*************************************************************************
  119. * do_sdrc_init(): initialize the SDRAM for use.
  120. * -code sets up SDRAM basic SDRC timings for CS0
  121. * -optimal settings can be placed here, or redone after i2c
  122. * inspection of board info
  123. *
  124. * - code called once in C-Stack only context for CS0 and a possible 2nd
  125. * time depending on memory configuration from stack+global context
  126. **************************************************************************/
  127. void do_sdrc_init(u32 cs, u32 early)
  128. {
  129. struct sdrc_actim *sdrc_actim_base;
  130. if(cs)
  131. sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
  132. else
  133. sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
  134. if (early) {
  135. /* reset sdrc controller */
  136. writel(SOFTRESET, &sdrc_base->sysconfig);
  137. wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
  138. 12000000);
  139. writel(0, &sdrc_base->sysconfig);
  140. /* setup sdrc to ball mux */
  141. writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
  142. /* Disable Power Down of CKE cuz of 1 CKE on combo part */
  143. writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
  144. writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
  145. sdelay(0x20000);
  146. }
  147. writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
  148. RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
  149. DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
  150. writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
  151. writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
  152. writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
  153. writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
  154. writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
  155. writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
  156. writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
  157. /*
  158. * CAS latency 3, Write Burst = Read Burst, Serial Mode,
  159. * Burst length = 4
  160. */
  161. writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
  162. if (!mem_ok(cs))
  163. writel(0, &sdrc_base->cs[cs].mcfg);
  164. }
  165. void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  166. u32 size)
  167. {
  168. writel(0, &cs->config7);
  169. sdelay(1000);
  170. /* Delay for settling */
  171. writel(gpmc_config[0], &cs->config1);
  172. writel(gpmc_config[1], &cs->config2);
  173. writel(gpmc_config[2], &cs->config3);
  174. writel(gpmc_config[3], &cs->config4);
  175. writel(gpmc_config[4], &cs->config5);
  176. writel(gpmc_config[5], &cs->config6);
  177. /* Enable the config */
  178. writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  179. (1 << 6)), &cs->config7);
  180. sdelay(2000);
  181. }
  182. /*****************************************************
  183. * gpmc_init(): init gpmc bus
  184. * Init GPMC for x16, MuxMode (SDRAM in x32).
  185. * This code can only be executed from SRAM or SDRAM.
  186. *****************************************************/
  187. void gpmc_init(void)
  188. {
  189. /* putting a blanket check on GPMC based on ZeBu for now */
  190. gpmc_cfg = (struct gpmc *)GPMC_BASE;
  191. #if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
  192. const u32 *gpmc_config = NULL;
  193. u32 base = 0;
  194. u32 size = 0;
  195. #if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
  196. u32 f_off = CONFIG_SYS_MONITOR_LEN;
  197. u32 f_sec = 0;
  198. #endif
  199. #endif
  200. u32 config = 0;
  201. /* global settings */
  202. writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
  203. writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
  204. config = readl(&gpmc_cfg->config);
  205. config &= (~0xf00);
  206. writel(config, &gpmc_cfg->config);
  207. /*
  208. * Disable the GPMC0 config set by ROM code
  209. * It conflicts with our MPDB (both at 0x08000000)
  210. */
  211. writel(0, &gpmc_cfg->cs[0].config7);
  212. sdelay(1000);
  213. #if defined(CONFIG_CMD_NAND) /* CS 0 */
  214. gpmc_config = gpmc_m_nand;
  215. base = PISMO1_NAND_BASE;
  216. size = PISMO1_NAND_SIZE;
  217. enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
  218. #if defined(CONFIG_ENV_IS_IN_NAND)
  219. f_off = SMNAND_ENV_OFFSET;
  220. f_sec = (128 << 10); /* 128 KiB */
  221. /* env setup */
  222. boot_flash_base = base;
  223. boot_flash_off = f_off;
  224. boot_flash_sec = f_sec;
  225. boot_flash_env_addr = f_off;
  226. #endif
  227. #endif
  228. #if defined(CONFIG_CMD_ONENAND)
  229. gpmc_config = gpmc_onenand;
  230. base = PISMO1_ONEN_BASE;
  231. size = PISMO1_ONEN_SIZE;
  232. enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
  233. #if defined(CONFIG_ENV_IS_IN_ONENAND)
  234. f_off = ONENAND_ENV_OFFSET;
  235. f_sec = (128 << 10); /* 128 KiB */
  236. /* env setup */
  237. boot_flash_base = base;
  238. boot_flash_off = f_off;
  239. boot_flash_sec = f_sec;
  240. boot_flash_env_addr = f_off;
  241. #endif
  242. #endif
  243. }