README.sbc8548 8.1 KB

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  1. Intro:
  2. ======
  3. The SBC8548 is a stand alone single board computer with a 1GHz
  4. MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
  5. memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
  6. and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
  7. ethernet connections.
  8. U-boot Configuration:
  9. =====================
  10. The following possible u-boot configuration targets are available:
  11. 1) sbc8548_config
  12. 2) sbc8548_PCI_33_config
  13. 3) sbc8548_PCI_66_config
  14. 4) sbc8548_PCI_33_PCIE_config
  15. 5) sbc8548_PCI_66_PCIE_config
  16. Generally speaking, most people should choose to use #5. Details
  17. of each choice are listed below.
  18. Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
  19. will be left empty (M66EN high), and so the board will operate with
  20. a base clock of 66MHz. Note that you need both PCI enabled in u-boot
  21. and linux in order to have functional PCI under linux.
  22. The second enables PCI support and builds for a 33MHz clock rate. Note
  23. that if a 33MHz 32bit card is inserted in the slot, then the whole board
  24. will clock down to a 33MHz base clock instead of the default 66MHz. This
  25. will change the baud clocks and mess up your serial console output if you
  26. were previously running at 66MHz. If you want to use a 33MHz PCI card,
  27. then you should build a U-Boot with a _PCI_33_ config and store this
  28. to flash prior to powering down the board and inserting the 33MHz PCI
  29. card. [The above discussion assumes that the SW2[1-4] has not been changed
  30. to reflect a different CCB:SYSCLK ratio]
  31. The third option builds PCI support in, and leaves the clocking at the
  32. default 66MHz. Options four and five are just repeats of option two
  33. and three, but with PCI-e support enabled as well.
  34. PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
  35. is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
  36. a 33MHz PCI configuration is currently untested.)
  37. => pci 0
  38. Scanning PCI devices on bus 0
  39. BusDevFun VendorId DeviceId Device Class Sub-Class
  40. _____________________________________________________________
  41. 00.00.00 0x1057 0x0012 Processor 0x20
  42. 00.01.00 0x8086 0x1026 Network controller 0x00
  43. => pci 1
  44. Scanning PCI devices on bus 1
  45. BusDevFun VendorId DeviceId Device Class Sub-Class
  46. _____________________________________________________________
  47. 01.00.00 0x1957 0x0012 Processor 0x20
  48. => pci 2
  49. Scanning PCI devices on bus 2
  50. BusDevFun VendorId DeviceId Device Class Sub-Class
  51. _____________________________________________________________
  52. 02.00.00 0x1148 0x9e00 Network controller 0x00
  53. =>
  54. Memory Size and using SPD:
  55. ==========================
  56. The default configuration uses hard coded memory configuration settings
  57. for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
  58. EEPROM data to read what memory is installed.
  59. There is a hardware errata, which causes the older local bus SDRAM
  60. SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
  61. that the SPD data can not be read reliably.
  62. If you want to upgrade to larger RAM size, you can simply enable
  63. #define CONFIG_SPD_EEPROM
  64. #define CONFIG_DDR_SPD
  65. in include/configs/sbc8548.h file. (The lines are already there
  66. but listed as #undef).
  67. Note that you will have to physically remove the LBC 128MB DIMM
  68. from the board's socket to resolve the above i2c address overlap
  69. issue and allow SPD autodetection of RAM to work.
  70. Updating U-boot with U-boot:
  71. ============================
  72. Note that versions of u-boot up to and including 2009.08 had u-boot stored
  73. at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
  74. 0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
  75. update u-boot with u-boot and it uses the old address, you will render
  76. your board inoperable, and you will require JTAG recovery.
  77. The following steps list how to update with the current address:
  78. tftp u-boot.bin
  79. md 200000 10
  80. protect off all
  81. erase fffa0000 ffffffff
  82. cp.b 200000 fffa0000 60000
  83. md fffa0000 10
  84. protect on all
  85. The "md" steps in the above are just a precautionary step that allow
  86. you to confirm the u-boot version that was downloaded, and then confirm
  87. that it was copied to flash.
  88. The above assumes that you are using the default board settings which
  89. have u-boot in the 8MB flash, tied to /CS0.
  90. If you are running the default 8MB /CS0 settings but want to store an
  91. image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
  92. (as a backup, etc) then the steps will become:
  93. tftp u-boot.bin
  94. md 200000 10
  95. protect off all
  96. era eff00000 efffffff
  97. cp.b 200000 eff00000 100000
  98. md eff00000 10
  99. protect on all
  100. Finally, if you are running the alternate 64MB /CS0 settings and want
  101. to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
  102. enabled) the steps will become:
  103. tftp u-boot.bin
  104. md 200000 10
  105. protect off all
  106. era fff00000 ffffffff
  107. cp.b 200000 fff00000 100000
  108. md fff00000 10
  109. protect on all
  110. Hardware Reference:
  111. ===================
  112. The following contains some summary information on hardware settings
  113. that are relevant to u-boot, based on the board manual. For the
  114. most up to date and complete details of the board, please request the
  115. reference manual ERG-00327-001.pdf from www.windriver.com
  116. Boot flash:
  117. intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
  118. Sodimm flash:
  119. intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
  120. Note that this address reflects the default setting for
  121. the JTAG debugging tools, but since the alignment is
  122. rather inconvenient, u-boot puts it at 0xec00_0000.
  123. Jumpers:
  124. Jumper Name ON OFF
  125. ----------------------------------------------------------------
  126. JP12 CS0/CS6 swap see note[*] see note[*]
  127. JP13 SODIMM flash write OK writes disabled
  128. write prot.
  129. JP14 HRESET/TRST joined isolated
  130. JP15 PWR ON when AC pwr use S1 for on/off
  131. JP16 Demo LEDs lit not lit
  132. JP19 PCI mode PCI PCI-X
  133. [*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
  134. onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
  135. is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
  136. SODIMM flash and /CS6 is for the boot flash. Note that in this
  137. alternate setting, you also need to switch SW2.8 to ON.
  138. See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
  139. and boot u-boot from the 64MB SODIMM
  140. Switches:
  141. The defaults are marked with a *
  142. Name Desc. ON OFF
  143. ------------------------------------------------------------------
  144. S1 Pwr toggle n/a n/a
  145. SW2.1 CFG_SYS_PLL0 1 0*
  146. SW2.2 CFG_SYS_PLL1 1* 0
  147. SW2.3 CFG_SYS_PLL2 1* 0
  148. SW2.4 CFG_SYS_PLL3 1 0*
  149. SW2.5 CFG_CORE_PLL0 1* 0
  150. SW2.6 CFG_CORE_PLL1 1 0*
  151. SW2.7 CFG_CORE_PLL2 1* 0
  152. SW2.8 CFG_ROM_LOC1 1 0*
  153. SW3.1 CFG_HOST_AGT0 1* 0
  154. SW3.2 CFG_HOST_AGT1 1* 0
  155. SW3.3 CFG_HOST_AGT2 1* 0
  156. SW3.4 CFG_IO_PORTS0 1* 0
  157. SW3.5 CFG_IO_PORTS0 1 0*
  158. SW3.6 CFG_IO_PORTS0 1 0*
  159. SerDes CLK(MHz) SW5.1 SW5.2
  160. ----------------------------------------------
  161. 25 0 0
  162. 100* 1 0
  163. 125 0 1
  164. 200 1 1
  165. SerDes CLK spread SW5.3 SW5.4
  166. ----------------------------------------------
  167. +/- 0.25% 0 0
  168. -0.50% 1 0
  169. -0.75% 0 1
  170. No Spread* 1 1
  171. SW4 settings are readable from the EPLD and are currently not used for
  172. any hardware settings (i.e. user configuration switches).
  173. LEDs:
  174. Name Desc. ON OFF
  175. ------------------------------------------------------------------
  176. D13 PCI/PCI-X PCI-X PCI
  177. D14 3.3V PWR 3.3V no power
  178. D15 SYSCLK 66MHz 33MHz
  179. Default Memory Map:
  180. start end CS<n> width Desc.
  181. ----------------------------------------------------------------------
  182. 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
  183. f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
  184. f800_0000 f8b0_1fff CS5 - EPLD
  185. fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
  186. ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
  187. [*] fb80 represents the default programmed by WR JTAG register files,
  188. but u-boot places the flash at either ec00 or fc00 based on JP12.
  189. The EPLD on CS5 demuxes the following devices at the following offsets:
  190. offset size width device
  191. --------------------------------------------------------
  192. 0 1fff 8 7 segment display LED
  193. 10_0000 1fff 4 user switches
  194. 30_0000 1fff 4 HW Rev. register
  195. b0_0000 1fff 8 8kB EEPROM