io.c 4.0 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <asm/processor.h>
  26. #include <asm/io.h>
  27. #include <asm/ppc4xx-gpio.h>
  28. #include <miiphy.h>
  29. #include "../common/fpga.h"
  30. #define PHYREG_CONTROL 0
  31. #define PHYREG_PAGE_ADDRESS 22
  32. #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
  33. #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
  34. enum {
  35. REG_VERSIONS = 0x0002,
  36. REG_FPGA_FEATURES = 0x0004,
  37. REG_FPGA_VERSION = 0x0006,
  38. REG_QUAD_SERDES_RESET = 0x0012,
  39. };
  40. enum {
  41. UNITTYPE_CCD_SWITCH = 1,
  42. };
  43. enum {
  44. HWVER_100 = 0,
  45. HWVER_110 = 1,
  46. HWVER_121 = 2,
  47. HWVER_122 = 3,
  48. };
  49. int configure_gbit_phy(unsigned char addr)
  50. {
  51. unsigned short value;
  52. /* select page 2 */
  53. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  54. PHYREG_PAGE_ADDRESS, 0x0002))
  55. goto err_out;
  56. /* disable SGMII autonegotiation */
  57. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  58. PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
  59. goto err_out;
  60. /* select page 0 */
  61. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  62. PHYREG_PAGE_ADDRESS, 0x0000))
  63. goto err_out;
  64. /* switch from powerdown to normal operation */
  65. if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  66. PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
  67. goto err_out;
  68. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  69. PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
  70. goto err_out;
  71. /* reset phy so settings take effect */
  72. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  73. PHYREG_CONTROL, 0x9140))
  74. goto err_out;
  75. return 0;
  76. err_out:
  77. printf("Error writing to the PHY addr=%02x\n", addr);
  78. return -1;
  79. }
  80. /*
  81. * Check Board Identity:
  82. */
  83. int checkboard(void)
  84. {
  85. char *s = getenv("serial#");
  86. u16 versions = fpga_get_reg(REG_VERSIONS);
  87. u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
  88. u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
  89. unsigned unit_type;
  90. unsigned hardware_version;
  91. unsigned feature_channels;
  92. unsigned feature_expansion;
  93. unit_type = (versions & 0xf000) >> 12;
  94. hardware_version = versions & 0x000f;
  95. feature_channels = fpga_features & 0x007f;
  96. feature_expansion = fpga_features & (1<<15);
  97. printf("Board: ");
  98. printf("CATCenter Io");
  99. if (s != NULL) {
  100. puts(", serial# ");
  101. puts(s);
  102. }
  103. puts("\n ");
  104. switch (unit_type) {
  105. case UNITTYPE_CCD_SWITCH:
  106. printf("CCD-Switch");
  107. break;
  108. default:
  109. printf("UnitType %d(not supported)", unit_type);
  110. break;
  111. }
  112. switch (hardware_version) {
  113. case HWVER_100:
  114. printf(" HW-Ver 1.00\n");
  115. break;
  116. case HWVER_110:
  117. printf(" HW-Ver 1.10\n");
  118. break;
  119. case HWVER_121:
  120. printf(" HW-Ver 1.21\n");
  121. break;
  122. case HWVER_122:
  123. printf(" HW-Ver 1.22\n");
  124. break;
  125. default:
  126. printf(" HW-Ver %d(not supported)\n",
  127. hardware_version);
  128. break;
  129. }
  130. printf(" FPGA V %d.%02d, features:",
  131. fpga_version / 100, fpga_version % 100);
  132. printf(" %d channel(s)", feature_channels);
  133. printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
  134. return 0;
  135. }
  136. /*
  137. * setup Gbit PHYs
  138. */
  139. int last_stage_init(void)
  140. {
  141. unsigned int k;
  142. miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
  143. bb_miiphy_read, bb_miiphy_write);
  144. for (k = 0; k < 32; ++k)
  145. configure_gbit_phy(k);
  146. /* take fpga serdes blocks out of reset */
  147. fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
  148. return 0;
  149. }