usb_ohci.c 43 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
  3. *
  4. * (C) Copyright 2003-2004
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * (C) Copyright 2004
  8. * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. *
  28. * Note: Part of this code has been derived from linux
  29. *
  30. */
  31. /*
  32. * IMPORTANT NOTES
  33. * 1 - this driver is intended for use with USB Mass Storage Devices
  34. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  35. */
  36. #include <common.h>
  37. #ifdef CONFIG_USB_OHCI
  38. #include <malloc.h>
  39. #include <usb.h>
  40. #include "usb_ohci.h"
  41. #include <mpc5xxx.h>
  42. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  43. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  44. #undef DEBUG
  45. #undef SHOW_INFO
  46. #undef OHCI_FILL_TRACE
  47. /* For initializing controller (mask in an HCFS mode too) */
  48. #define OHCI_CONTROL_INIT \
  49. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  50. #define readl(a) (*((vu_long *)(a)))
  51. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  52. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  53. #ifdef DEBUG
  54. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  55. #else
  56. #define dbg(format, arg...) do {} while(0)
  57. #endif /* DEBUG */
  58. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  59. #ifdef SHOW_INFO
  60. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  61. #else
  62. #define info(format, arg...) do {} while(0)
  63. #endif
  64. #define m16_swap(x) swap_16(x)
  65. #define m32_swap(x) swap_32(x)
  66. #ifdef CONFIG_MPC5200
  67. #define ohci_cpu_to_le16(x) (x)
  68. #define ohci_cpu_to_le32(x) (x)
  69. #else
  70. #define ohci_cpu_to_le16(x) swap_16(x)
  71. #define ohci_cpu_to_le32(x) swap_32(x)
  72. #endif
  73. /* global ohci_t */
  74. static ohci_t gohci;
  75. /* this must be aligned to a 256 byte boundary */
  76. struct ohci_hcca ghcca[1];
  77. /* a pointer to the aligned storage */
  78. struct ohci_hcca *phcca;
  79. /* this allocates EDs for all possible endpoints */
  80. struct ohci_device ohci_dev;
  81. /* urb_priv */
  82. urb_priv_t urb_priv;
  83. /* RHSC flag */
  84. int got_rhsc;
  85. /* device which was disconnected */
  86. struct usb_device *devgone;
  87. /*-------------------------------------------------------------------------*/
  88. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  89. * The erratum (#4) description is incorrect. AMD's workaround waits
  90. * till some bits (mostly reserved) are clear; ok for all revs.
  91. */
  92. #define OHCI_QUIRK_AMD756 0xabcd
  93. #define read_roothub(hc, register, mask) ({ \
  94. u32 temp = readl (&hc->regs->roothub.register); \
  95. if (hc->flags & OHCI_QUIRK_AMD756) \
  96. while (temp & mask) \
  97. temp = readl (&hc->regs->roothub.register); \
  98. temp; })
  99. static u32 roothub_a (struct ohci *hc)
  100. { return read_roothub (hc, a, 0xfc0fe000); }
  101. static inline u32 roothub_b (struct ohci *hc)
  102. { return readl (&hc->regs->roothub.b); }
  103. static inline u32 roothub_status (struct ohci *hc)
  104. { return readl (&hc->regs->roothub.status); }
  105. static u32 roothub_portstatus (struct ohci *hc, int i)
  106. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  107. /* forward declaration */
  108. static int hc_interrupt (void);
  109. static void
  110. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  111. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  112. /*-------------------------------------------------------------------------*
  113. * URB support functions
  114. *-------------------------------------------------------------------------*/
  115. /* free HCD-private data associated with this URB */
  116. static void urb_free_priv (urb_priv_t * urb)
  117. {
  118. int i;
  119. int last;
  120. struct td * td;
  121. last = urb->length - 1;
  122. if (last >= 0) {
  123. for (i = 0; i <= last; i++) {
  124. td = urb->td[i];
  125. if (td) {
  126. td->usb_dev = NULL;
  127. urb->td[i] = NULL;
  128. }
  129. }
  130. }
  131. }
  132. /*-------------------------------------------------------------------------*/
  133. #ifdef DEBUG
  134. static int sohci_get_current_frame_number (struct usb_device * dev);
  135. /* debug| print the main components of an URB
  136. * small: 0) header + data packets 1) just header */
  137. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  138. int transfer_len, struct devrequest * setup, char * str, int small)
  139. {
  140. urb_priv_t * purb = &urb_priv;
  141. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  142. str,
  143. sohci_get_current_frame_number (dev),
  144. usb_pipedevice (pipe),
  145. usb_pipeendpoint (pipe),
  146. usb_pipeout (pipe)? 'O': 'I',
  147. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  148. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  149. purb->actual_length,
  150. transfer_len, dev->status);
  151. #ifdef OHCI_VERBOSE_DEBUG
  152. if (!small) {
  153. int i, len;
  154. if (usb_pipecontrol (pipe)) {
  155. printf (__FILE__ ": cmd(8):");
  156. for (i = 0; i < 8 ; i++)
  157. printf (" %02x", ((__u8 *) setup) [i]);
  158. printf ("\n");
  159. }
  160. if (transfer_len > 0 && buffer) {
  161. printf (__FILE__ ": data(%d/%d):",
  162. purb->actual_length,
  163. transfer_len);
  164. len = usb_pipeout (pipe)?
  165. transfer_len: purb->actual_length;
  166. for (i = 0; i < 16 && i < len; i++)
  167. printf (" %02x", ((__u8 *) buffer) [i]);
  168. printf ("%s\n", i < len? "...": "");
  169. }
  170. }
  171. #endif
  172. }
  173. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  174. void ep_print_int_eds (ohci_t *ohci, char * str) {
  175. int i, j;
  176. __u32 * ed_p;
  177. for (i= 0; i < 32; i++) {
  178. j = 5;
  179. ed_p = &(ohci->hcca->int_table [i]);
  180. if (*ed_p == 0)
  181. continue;
  182. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  183. while (*ed_p != 0 && j--) {
  184. ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
  185. printf (" ed: %4x;", ed->hwINFO);
  186. ed_p = &ed->hwNextED;
  187. }
  188. printf ("\n");
  189. }
  190. }
  191. static void ohci_dump_intr_mask (char *label, __u32 mask)
  192. {
  193. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  194. label,
  195. mask,
  196. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  197. (mask & OHCI_INTR_OC) ? " OC" : "",
  198. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  199. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  200. (mask & OHCI_INTR_UE) ? " UE" : "",
  201. (mask & OHCI_INTR_RD) ? " RD" : "",
  202. (mask & OHCI_INTR_SF) ? " SF" : "",
  203. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  204. (mask & OHCI_INTR_SO) ? " SO" : ""
  205. );
  206. }
  207. static void maybe_print_eds (char *label, __u32 value)
  208. {
  209. ed_t *edp = (ed_t *)value;
  210. if (value) {
  211. dbg ("%s %08x", label, value);
  212. dbg ("%08x", edp->hwINFO);
  213. dbg ("%08x", edp->hwTailP);
  214. dbg ("%08x", edp->hwHeadP);
  215. dbg ("%08x", edp->hwNextED);
  216. }
  217. }
  218. static char * hcfs2string (int state)
  219. {
  220. switch (state) {
  221. case OHCI_USB_RESET: return "reset";
  222. case OHCI_USB_RESUME: return "resume";
  223. case OHCI_USB_OPER: return "operational";
  224. case OHCI_USB_SUSPEND: return "suspend";
  225. }
  226. return "?";
  227. }
  228. /* dump control and status registers */
  229. static void ohci_dump_status (ohci_t *controller)
  230. {
  231. struct ohci_regs *regs = controller->regs;
  232. __u32 temp;
  233. temp = readl (&regs->revision) & 0xff;
  234. if (temp != 0x10)
  235. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  236. temp = readl (&regs->control);
  237. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  238. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  239. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  240. (temp & OHCI_CTRL_IR) ? " IR" : "",
  241. hcfs2string (temp & OHCI_CTRL_HCFS),
  242. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  243. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  244. (temp & OHCI_CTRL_IE) ? " IE" : "",
  245. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  246. temp & OHCI_CTRL_CBSR
  247. );
  248. temp = readl (&regs->cmdstatus);
  249. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  250. (temp & OHCI_SOC) >> 16,
  251. (temp & OHCI_OCR) ? " OCR" : "",
  252. (temp & OHCI_BLF) ? " BLF" : "",
  253. (temp & OHCI_CLF) ? " CLF" : "",
  254. (temp & OHCI_HCR) ? " HCR" : ""
  255. );
  256. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  257. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  258. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  259. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  260. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  261. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  262. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  263. maybe_print_eds ("donehead", readl (&regs->donehead));
  264. }
  265. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  266. {
  267. __u32 temp, ndp, i;
  268. temp = roothub_a (controller);
  269. ndp = (temp & RH_A_NDP);
  270. if (verbose) {
  271. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  272. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  273. (temp & RH_A_NOCP) ? " NOCP" : "",
  274. (temp & RH_A_OCPM) ? " OCPM" : "",
  275. (temp & RH_A_DT) ? " DT" : "",
  276. (temp & RH_A_NPS) ? " NPS" : "",
  277. (temp & RH_A_PSM) ? " PSM" : "",
  278. ndp
  279. );
  280. temp = roothub_b (controller);
  281. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  282. temp,
  283. (temp & RH_B_PPCM) >> 16,
  284. (temp & RH_B_DR)
  285. );
  286. temp = roothub_status (controller);
  287. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  288. temp,
  289. (temp & RH_HS_CRWE) ? " CRWE" : "",
  290. (temp & RH_HS_OCIC) ? " OCIC" : "",
  291. (temp & RH_HS_LPSC) ? " LPSC" : "",
  292. (temp & RH_HS_DRWE) ? " DRWE" : "",
  293. (temp & RH_HS_OCI) ? " OCI" : "",
  294. (temp & RH_HS_LPS) ? " LPS" : ""
  295. );
  296. }
  297. for (i = 0; i < ndp; i++) {
  298. temp = roothub_portstatus (controller, i);
  299. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  300. i,
  301. temp,
  302. (temp & RH_PS_PRSC) ? " PRSC" : "",
  303. (temp & RH_PS_OCIC) ? " OCIC" : "",
  304. (temp & RH_PS_PSSC) ? " PSSC" : "",
  305. (temp & RH_PS_PESC) ? " PESC" : "",
  306. (temp & RH_PS_CSC) ? " CSC" : "",
  307. (temp & RH_PS_LSDA) ? " LSDA" : "",
  308. (temp & RH_PS_PPS) ? " PPS" : "",
  309. (temp & RH_PS_PRS) ? " PRS" : "",
  310. (temp & RH_PS_POCI) ? " POCI" : "",
  311. (temp & RH_PS_PSS) ? " PSS" : "",
  312. (temp & RH_PS_PES) ? " PES" : "",
  313. (temp & RH_PS_CCS) ? " CCS" : ""
  314. );
  315. }
  316. }
  317. static void ohci_dump (ohci_t *controller, int verbose)
  318. {
  319. dbg ("OHCI controller usb-%s state", controller->slot_name);
  320. /* dumps some of the state we know about */
  321. ohci_dump_status (controller);
  322. if (verbose)
  323. ep_print_int_eds (controller, "hcca");
  324. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  325. ohci_dump_roothub (controller, 1);
  326. }
  327. #endif /* DEBUG */
  328. /*-------------------------------------------------------------------------*
  329. * Interface functions (URB)
  330. *-------------------------------------------------------------------------*/
  331. /* get a transfer request */
  332. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  333. int transfer_len, struct devrequest *setup, int interval)
  334. {
  335. ohci_t *ohci;
  336. ed_t * ed;
  337. urb_priv_t *purb_priv;
  338. int i, size = 0;
  339. ohci = &gohci;
  340. /* when controller's hung, permit only roothub cleanup attempts
  341. * such as powering down ports */
  342. if (ohci->disabled) {
  343. err("sohci_submit_job: EPIPE");
  344. return -1;
  345. }
  346. /* every endpoint has a ed, locate and fill it */
  347. if (!(ed = ep_add_ed (dev, pipe))) {
  348. err("sohci_submit_job: ENOMEM");
  349. return -1;
  350. }
  351. /* for the private part of the URB we need the number of TDs (size) */
  352. switch (usb_pipetype (pipe)) {
  353. case PIPE_BULK: /* one TD for every 4096 Byte */
  354. size = (transfer_len - 1) / 4096 + 1;
  355. break;
  356. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  357. size = (transfer_len == 0)? 2:
  358. (transfer_len - 1) / 4096 + 3;
  359. break;
  360. }
  361. if (size >= (N_URB_TD - 1)) {
  362. err("need %d TDs, only have %d", size, N_URB_TD);
  363. return -1;
  364. }
  365. purb_priv = &urb_priv;
  366. purb_priv->pipe = pipe;
  367. /* fill the private part of the URB */
  368. purb_priv->length = size;
  369. purb_priv->ed = ed;
  370. purb_priv->actual_length = 0;
  371. /* allocate the TDs */
  372. /* note that td[0] was allocated in ep_add_ed */
  373. for (i = 0; i < size; i++) {
  374. purb_priv->td[i] = td_alloc (dev);
  375. if (!purb_priv->td[i]) {
  376. purb_priv->length = i;
  377. urb_free_priv (purb_priv);
  378. err("sohci_submit_job: ENOMEM");
  379. return -1;
  380. }
  381. }
  382. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  383. urb_free_priv (purb_priv);
  384. err("sohci_submit_job: EINVAL");
  385. return -1;
  386. }
  387. /* link the ed into a chain if is not already */
  388. if (ed->state != ED_OPER)
  389. ep_link (ohci, ed);
  390. /* fill the TDs and link it to the ed */
  391. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  392. return 0;
  393. }
  394. /*-------------------------------------------------------------------------*/
  395. #ifdef DEBUG
  396. /* tell us the current USB frame number */
  397. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  398. {
  399. ohci_t *ohci = &gohci;
  400. return ohci_cpu_to_le16 (ohci->hcca->frame_no);
  401. }
  402. #endif
  403. /*-------------------------------------------------------------------------*
  404. * ED handling functions
  405. *-------------------------------------------------------------------------*/
  406. /* link an ed into one of the HC chains */
  407. static int ep_link (ohci_t *ohci, ed_t *edi)
  408. {
  409. volatile ed_t *ed = edi;
  410. ed->state = ED_OPER;
  411. switch (ed->type) {
  412. case PIPE_CONTROL:
  413. ed->hwNextED = 0;
  414. if (ohci->ed_controltail == NULL) {
  415. writel (ed, &ohci->regs->ed_controlhead);
  416. } else {
  417. ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  418. }
  419. ed->ed_prev = ohci->ed_controltail;
  420. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  421. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  422. ohci->hc_control |= OHCI_CTRL_CLE;
  423. writel (ohci->hc_control, &ohci->regs->control);
  424. }
  425. ohci->ed_controltail = edi;
  426. break;
  427. case PIPE_BULK:
  428. ed->hwNextED = 0;
  429. if (ohci->ed_bulktail == NULL) {
  430. writel (ed, &ohci->regs->ed_bulkhead);
  431. } else {
  432. ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  433. }
  434. ed->ed_prev = ohci->ed_bulktail;
  435. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  436. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  437. ohci->hc_control |= OHCI_CTRL_BLE;
  438. writel (ohci->hc_control, &ohci->regs->control);
  439. }
  440. ohci->ed_bulktail = edi;
  441. break;
  442. }
  443. return 0;
  444. }
  445. /*-------------------------------------------------------------------------*/
  446. /* unlink an ed from one of the HC chains.
  447. * just the link to the ed is unlinked.
  448. * the link from the ed still points to another operational ed or 0
  449. * so the HC can eventually finish the processing of the unlinked ed */
  450. static int ep_unlink (ohci_t *ohci, ed_t *edi)
  451. {
  452. volatile ed_t *ed = edi;
  453. ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
  454. switch (ed->type) {
  455. case PIPE_CONTROL:
  456. if (ed->ed_prev == NULL) {
  457. if (!ed->hwNextED) {
  458. ohci->hc_control &= ~OHCI_CTRL_CLE;
  459. writel (ohci->hc_control, &ohci->regs->control);
  460. }
  461. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  462. } else {
  463. ed->ed_prev->hwNextED = ed->hwNextED;
  464. }
  465. if (ohci->ed_controltail == ed) {
  466. ohci->ed_controltail = ed->ed_prev;
  467. } else {
  468. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  469. }
  470. break;
  471. case PIPE_BULK:
  472. if (ed->ed_prev == NULL) {
  473. if (!ed->hwNextED) {
  474. ohci->hc_control &= ~OHCI_CTRL_BLE;
  475. writel (ohci->hc_control, &ohci->regs->control);
  476. }
  477. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  478. } else {
  479. ed->ed_prev->hwNextED = ed->hwNextED;
  480. }
  481. if (ohci->ed_bulktail == ed) {
  482. ohci->ed_bulktail = ed->ed_prev;
  483. } else {
  484. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  485. }
  486. break;
  487. }
  488. ed->state = ED_UNLINK;
  489. return 0;
  490. }
  491. /*-------------------------------------------------------------------------*/
  492. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  493. * but the USB stack is a little bit stateless so we do it at every transaction
  494. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  495. * in all other cases the state is left unchanged
  496. * the ed info fields are setted anyway even though most of them should not change */
  497. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  498. {
  499. td_t *td;
  500. ed_t *ed_ret;
  501. volatile ed_t *ed;
  502. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  503. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  504. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  505. err("ep_add_ed: pending delete");
  506. /* pending delete request */
  507. return NULL;
  508. }
  509. if (ed->state == ED_NEW) {
  510. ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
  511. /* dummy td; end of td list for ed */
  512. td = td_alloc (usb_dev);
  513. ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
  514. ed->hwHeadP = ed->hwTailP;
  515. ed->state = ED_UNLINK;
  516. ed->type = usb_pipetype (pipe);
  517. ohci_dev.ed_cnt++;
  518. }
  519. ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
  520. | usb_pipeendpoint (pipe) << 7
  521. | (usb_pipeisoc (pipe)? 0x8000: 0)
  522. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  523. | usb_pipeslow (pipe) << 13
  524. | usb_maxpacket (usb_dev, pipe) << 16);
  525. return ed_ret;
  526. }
  527. /*-------------------------------------------------------------------------*
  528. * TD handling functions
  529. *-------------------------------------------------------------------------*/
  530. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  531. static void td_fill (ohci_t *ohci, unsigned int info,
  532. void *data, int len,
  533. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  534. {
  535. volatile td_t *td, *td_pt;
  536. #ifdef OHCI_FILL_TRACE
  537. int i;
  538. #endif
  539. if (index > urb_priv->length) {
  540. err("index > length");
  541. return;
  542. }
  543. /* use this td as the next dummy */
  544. td_pt = urb_priv->td [index];
  545. td_pt->hwNextTD = 0;
  546. /* fill the old dummy TD */
  547. td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
  548. td->ed = urb_priv->ed;
  549. td->next_dl_td = NULL;
  550. td->index = index;
  551. td->data = (__u32)data;
  552. #ifdef OHCI_FILL_TRACE
  553. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  554. for (i = 0; i < len; i++)
  555. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  556. printf("\n");
  557. }
  558. #endif
  559. if (!len)
  560. data = 0;
  561. td->hwINFO = ohci_cpu_to_le32 (info);
  562. td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
  563. if (data)
  564. td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
  565. else
  566. td->hwBE = 0;
  567. td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
  568. td->hwPSW [0] = ohci_cpu_to_le16 (((__u32)data & 0x0FFF) | 0xE000);
  569. /* append to queue */
  570. td->ed->hwTailP = td->hwNextTD;
  571. }
  572. /*-------------------------------------------------------------------------*/
  573. /* prepare all TDs of a transfer */
  574. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  575. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  576. {
  577. ohci_t *ohci = &gohci;
  578. int data_len = transfer_len;
  579. void *data;
  580. int cnt = 0;
  581. __u32 info = 0;
  582. unsigned int toggle = 0;
  583. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  584. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  585. toggle = TD_T_TOGGLE;
  586. } else {
  587. toggle = TD_T_DATA0;
  588. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  589. }
  590. urb->td_cnt = 0;
  591. if (data_len)
  592. data = buffer;
  593. else
  594. data = 0;
  595. switch (usb_pipetype (pipe)) {
  596. case PIPE_BULK:
  597. info = usb_pipeout (pipe)?
  598. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  599. while(data_len > 4096) {
  600. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  601. data += 4096; data_len -= 4096; cnt++;
  602. }
  603. info = usb_pipeout (pipe)?
  604. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  605. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  606. cnt++;
  607. if (!ohci->sleeping)
  608. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  609. break;
  610. case PIPE_CONTROL:
  611. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  612. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  613. if (data_len > 0) {
  614. info = usb_pipeout (pipe)?
  615. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  616. /* NOTE: mishandles transfers >8K, some >4K */
  617. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  618. }
  619. info = usb_pipeout (pipe)?
  620. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  621. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  622. if (!ohci->sleeping)
  623. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  624. break;
  625. }
  626. if (urb->length != cnt)
  627. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  628. }
  629. /*-------------------------------------------------------------------------*
  630. * Done List handling functions
  631. *-------------------------------------------------------------------------*/
  632. /* calculate the transfer length and update the urb */
  633. static void dl_transfer_length(td_t * td)
  634. {
  635. __u32 tdINFO, tdBE, tdCBP;
  636. urb_priv_t *lurb_priv = &urb_priv;
  637. tdINFO = ohci_cpu_to_le32 (td->hwINFO);
  638. tdBE = ohci_cpu_to_le32 (td->hwBE);
  639. tdCBP = ohci_cpu_to_le32 (td->hwCBP);
  640. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  641. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  642. if (tdBE != 0) {
  643. if (td->hwCBP == 0)
  644. lurb_priv->actual_length += tdBE - td->data + 1;
  645. else
  646. lurb_priv->actual_length += tdCBP - td->data;
  647. }
  648. }
  649. }
  650. /*-------------------------------------------------------------------------*/
  651. /* replies to the request have to be on a FIFO basis so
  652. * we reverse the reversed done-list */
  653. static td_t * dl_reverse_done_list (ohci_t *ohci)
  654. {
  655. __u32 td_list_hc;
  656. td_t *td_rev = NULL;
  657. td_t *td_list = NULL;
  658. urb_priv_t *lurb_priv = NULL;
  659. td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
  660. ohci->hcca->done_head = 0;
  661. while (td_list_hc) {
  662. td_list = (td_t *)td_list_hc;
  663. if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
  664. lurb_priv = &urb_priv;
  665. dbg(" USB-error/status: %x : %p",
  666. TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
  667. if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
  668. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  669. td_list->ed->hwHeadP =
  670. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
  671. (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
  672. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  673. } else
  674. td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
  675. }
  676. #ifdef CONFIG_MPC5200
  677. td_list->hwNextTD = 0;
  678. #endif
  679. }
  680. td_list->next_dl_td = td_rev;
  681. td_rev = td_list;
  682. td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
  683. }
  684. return td_list;
  685. }
  686. /*-------------------------------------------------------------------------*/
  687. /* td done list */
  688. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  689. {
  690. td_t *td_list_next = NULL;
  691. ed_t *ed;
  692. int cc = 0;
  693. int stat = 0xff;
  694. /* urb_t *urb; */
  695. urb_priv_t *lurb_priv;
  696. __u32 tdINFO, edHeadP, edTailP;
  697. while (td_list) {
  698. td_list_next = td_list->next_dl_td;
  699. lurb_priv = &urb_priv;
  700. tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
  701. ed = td_list->ed;
  702. dl_transfer_length(td_list);
  703. /* error code of transfer */
  704. cc = TD_CC_GET (tdINFO);
  705. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  706. if ((ed->state & (ED_OPER | ED_UNLINK))
  707. && (lurb_priv->state != URB_DEL)) {
  708. dbg("ConditionCode %#x", cc);
  709. stat = cc_to_error[cc];
  710. }
  711. }
  712. if (ed->state != ED_NEW) {
  713. edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
  714. edTailP = ohci_cpu_to_le32 (ed->hwTailP);
  715. /* unlink eds if they are not busy */
  716. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  717. ep_unlink (ohci, ed);
  718. }
  719. td_list = td_list_next;
  720. }
  721. return stat;
  722. }
  723. /*-------------------------------------------------------------------------*
  724. * Virtual Root Hub
  725. *-------------------------------------------------------------------------*/
  726. /* Device descriptor */
  727. static __u8 root_hub_dev_des[] =
  728. {
  729. 0x12, /* __u8 bLength; */
  730. 0x01, /* __u8 bDescriptorType; Device */
  731. 0x10, /* __u16 bcdUSB; v1.1 */
  732. 0x01,
  733. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  734. 0x00, /* __u8 bDeviceSubClass; */
  735. 0x00, /* __u8 bDeviceProtocol; */
  736. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  737. 0x00, /* __u16 idVendor; */
  738. 0x00,
  739. 0x00, /* __u16 idProduct; */
  740. 0x00,
  741. 0x00, /* __u16 bcdDevice; */
  742. 0x00,
  743. 0x00, /* __u8 iManufacturer; */
  744. 0x01, /* __u8 iProduct; */
  745. 0x00, /* __u8 iSerialNumber; */
  746. 0x01 /* __u8 bNumConfigurations; */
  747. };
  748. /* Configuration descriptor */
  749. static __u8 root_hub_config_des[] =
  750. {
  751. 0x09, /* __u8 bLength; */
  752. 0x02, /* __u8 bDescriptorType; Configuration */
  753. 0x19, /* __u16 wTotalLength; */
  754. 0x00,
  755. 0x01, /* __u8 bNumInterfaces; */
  756. 0x01, /* __u8 bConfigurationValue; */
  757. 0x00, /* __u8 iConfiguration; */
  758. 0x40, /* __u8 bmAttributes;
  759. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  760. 0x00, /* __u8 MaxPower; */
  761. /* interface */
  762. 0x09, /* __u8 if_bLength; */
  763. 0x04, /* __u8 if_bDescriptorType; Interface */
  764. 0x00, /* __u8 if_bInterfaceNumber; */
  765. 0x00, /* __u8 if_bAlternateSetting; */
  766. 0x01, /* __u8 if_bNumEndpoints; */
  767. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  768. 0x00, /* __u8 if_bInterfaceSubClass; */
  769. 0x00, /* __u8 if_bInterfaceProtocol; */
  770. 0x00, /* __u8 if_iInterface; */
  771. /* endpoint */
  772. 0x07, /* __u8 ep_bLength; */
  773. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  774. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  775. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  776. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  777. 0x00,
  778. 0xff /* __u8 ep_bInterval; 255 ms */
  779. };
  780. static unsigned char root_hub_str_index0[] =
  781. {
  782. 0x04, /* __u8 bLength; */
  783. 0x03, /* __u8 bDescriptorType; String-descriptor */
  784. 0x09, /* __u8 lang ID */
  785. 0x04, /* __u8 lang ID */
  786. };
  787. static unsigned char root_hub_str_index1[] =
  788. {
  789. 28, /* __u8 bLength; */
  790. 0x03, /* __u8 bDescriptorType; String-descriptor */
  791. 'O', /* __u8 Unicode */
  792. 0, /* __u8 Unicode */
  793. 'H', /* __u8 Unicode */
  794. 0, /* __u8 Unicode */
  795. 'C', /* __u8 Unicode */
  796. 0, /* __u8 Unicode */
  797. 'I', /* __u8 Unicode */
  798. 0, /* __u8 Unicode */
  799. ' ', /* __u8 Unicode */
  800. 0, /* __u8 Unicode */
  801. 'R', /* __u8 Unicode */
  802. 0, /* __u8 Unicode */
  803. 'o', /* __u8 Unicode */
  804. 0, /* __u8 Unicode */
  805. 'o', /* __u8 Unicode */
  806. 0, /* __u8 Unicode */
  807. 't', /* __u8 Unicode */
  808. 0, /* __u8 Unicode */
  809. ' ', /* __u8 Unicode */
  810. 0, /* __u8 Unicode */
  811. 'H', /* __u8 Unicode */
  812. 0, /* __u8 Unicode */
  813. 'u', /* __u8 Unicode */
  814. 0, /* __u8 Unicode */
  815. 'b', /* __u8 Unicode */
  816. 0, /* __u8 Unicode */
  817. };
  818. /* Hub class-specific descriptor is constructed dynamically */
  819. /*-------------------------------------------------------------------------*/
  820. #define OK(x) len = (x); break
  821. #ifdef DEBUG
  822. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  823. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  824. #else
  825. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  826. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  827. #endif
  828. #define RD_RH_STAT roothub_status(&gohci)
  829. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  830. /* request to virtual root hub */
  831. int rh_check_port_status(ohci_t *controller)
  832. {
  833. __u32 temp, ndp, i;
  834. int res;
  835. res = -1;
  836. temp = roothub_a (controller);
  837. ndp = (temp & RH_A_NDP);
  838. for (i = 0; i < ndp; i++) {
  839. temp = roothub_portstatus (controller, i);
  840. /* check for a device disconnect */
  841. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  842. (RH_PS_PESC | RH_PS_CSC)) &&
  843. ((temp & RH_PS_CCS) == 0)) {
  844. res = i;
  845. break;
  846. }
  847. }
  848. return res;
  849. }
  850. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  851. void *buffer, int transfer_len, struct devrequest *cmd)
  852. {
  853. void * data = buffer;
  854. int leni = transfer_len;
  855. int len = 0;
  856. int stat = 0;
  857. __u32 datab[4];
  858. __u8 *data_buf = (__u8 *)datab;
  859. __u16 bmRType_bReq;
  860. __u16 wValue;
  861. __u16 wIndex;
  862. __u16 wLength;
  863. #ifdef DEBUG
  864. urb_priv.actual_length = 0;
  865. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  866. #endif
  867. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  868. info("Root-Hub submit IRQ: NOT implemented");
  869. return 0;
  870. }
  871. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  872. wValue = m16_swap (cmd->value);
  873. wIndex = m16_swap (cmd->index);
  874. wLength = m16_swap (cmd->length);
  875. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  876. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  877. switch (bmRType_bReq) {
  878. /* Request Destination:
  879. without flags: Device,
  880. RH_INTERFACE: interface,
  881. RH_ENDPOINT: endpoint,
  882. RH_CLASS means HUB here,
  883. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  884. */
  885. case RH_GET_STATUS:
  886. *(__u16 *) data_buf = m16_swap (1); OK (2);
  887. case RH_GET_STATUS | RH_INTERFACE:
  888. *(__u16 *) data_buf = m16_swap (0); OK (2);
  889. case RH_GET_STATUS | RH_ENDPOINT:
  890. *(__u16 *) data_buf = m16_swap (0); OK (2);
  891. case RH_GET_STATUS | RH_CLASS:
  892. *(__u32 *) data_buf = m32_swap (
  893. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  894. OK (4);
  895. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  896. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  897. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  898. switch (wValue) {
  899. case (RH_ENDPOINT_STALL): OK (0);
  900. }
  901. break;
  902. case RH_CLEAR_FEATURE | RH_CLASS:
  903. switch (wValue) {
  904. case RH_C_HUB_LOCAL_POWER:
  905. OK(0);
  906. case (RH_C_HUB_OVER_CURRENT):
  907. WR_RH_STAT(RH_HS_OCIC); OK (0);
  908. }
  909. break;
  910. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  911. switch (wValue) {
  912. case (RH_PORT_ENABLE):
  913. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  914. case (RH_PORT_SUSPEND):
  915. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  916. case (RH_PORT_POWER):
  917. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  918. case (RH_C_PORT_CONNECTION):
  919. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  920. case (RH_C_PORT_ENABLE):
  921. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  922. case (RH_C_PORT_SUSPEND):
  923. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  924. case (RH_C_PORT_OVER_CURRENT):
  925. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  926. case (RH_C_PORT_RESET):
  927. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  928. }
  929. break;
  930. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  931. switch (wValue) {
  932. case (RH_PORT_SUSPEND):
  933. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  934. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  935. if (RD_RH_PORTSTAT & RH_PS_CCS)
  936. WR_RH_PORTSTAT (RH_PS_PRS);
  937. OK (0);
  938. case (RH_PORT_POWER):
  939. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  940. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  941. if (RD_RH_PORTSTAT & RH_PS_CCS)
  942. WR_RH_PORTSTAT (RH_PS_PES );
  943. OK (0);
  944. }
  945. break;
  946. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  947. case RH_GET_DESCRIPTOR:
  948. switch ((wValue & 0xff00) >> 8) {
  949. case (0x01): /* device descriptor */
  950. len = min_t(unsigned int,
  951. leni,
  952. min_t(unsigned int,
  953. sizeof (root_hub_dev_des),
  954. wLength));
  955. data_buf = root_hub_dev_des; OK(len);
  956. case (0x02): /* configuration descriptor */
  957. len = min_t(unsigned int,
  958. leni,
  959. min_t(unsigned int,
  960. sizeof (root_hub_config_des),
  961. wLength));
  962. data_buf = root_hub_config_des; OK(len);
  963. case (0x03): /* string descriptors */
  964. if(wValue==0x0300) {
  965. len = min_t(unsigned int,
  966. leni,
  967. min_t(unsigned int,
  968. sizeof (root_hub_str_index0),
  969. wLength));
  970. data_buf = root_hub_str_index0;
  971. OK(len);
  972. }
  973. if(wValue==0x0301) {
  974. len = min_t(unsigned int,
  975. leni,
  976. min_t(unsigned int,
  977. sizeof (root_hub_str_index1),
  978. wLength));
  979. data_buf = root_hub_str_index1;
  980. OK(len);
  981. }
  982. default:
  983. stat = USB_ST_STALLED;
  984. }
  985. break;
  986. case RH_GET_DESCRIPTOR | RH_CLASS:
  987. {
  988. __u32 temp = roothub_a (&gohci);
  989. data_buf [0] = 9; /* min length; */
  990. data_buf [1] = 0x29;
  991. data_buf [2] = temp & RH_A_NDP;
  992. data_buf [3] = 0;
  993. if (temp & RH_A_PSM) /* per-port power switching? */
  994. data_buf [3] |= 0x1;
  995. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  996. data_buf [3] |= 0x10;
  997. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  998. data_buf [3] |= 0x8;
  999. /* corresponds to data_buf[4-7] */
  1000. datab [1] = 0;
  1001. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1002. temp = roothub_b (&gohci);
  1003. data_buf [7] = temp & RH_B_DR;
  1004. if (data_buf [2] < 7) {
  1005. data_buf [8] = 0xff;
  1006. } else {
  1007. data_buf [0] += 2;
  1008. data_buf [8] = (temp & RH_B_DR) >> 8;
  1009. data_buf [10] = data_buf [9] = 0xff;
  1010. }
  1011. len = min_t(unsigned int, leni,
  1012. min_t(unsigned int, data_buf [0], wLength));
  1013. OK (len);
  1014. }
  1015. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1016. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1017. default:
  1018. dbg ("unsupported root hub command");
  1019. stat = USB_ST_STALLED;
  1020. }
  1021. #ifdef DEBUG
  1022. ohci_dump_roothub (&gohci, 1);
  1023. #endif
  1024. len = min_t(int, len, leni);
  1025. if (data != data_buf)
  1026. memcpy (data, data_buf, len);
  1027. dev->act_len = len;
  1028. dev->status = stat;
  1029. #ifdef DEBUG
  1030. if (transfer_len)
  1031. urb_priv.actual_length = transfer_len;
  1032. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1033. #endif
  1034. return stat;
  1035. }
  1036. /*-------------------------------------------------------------------------*/
  1037. /* common code for handling submit messages - used for all but root hub */
  1038. /* accesses. */
  1039. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1040. int transfer_len, struct devrequest *setup, int interval)
  1041. {
  1042. int stat = 0;
  1043. int maxsize = usb_maxpacket(dev, pipe);
  1044. int timeout;
  1045. /* device pulled? Shortcut the action. */
  1046. if (devgone == dev) {
  1047. dev->status = USB_ST_CRC_ERR;
  1048. return 0;
  1049. }
  1050. #ifdef DEBUG
  1051. urb_priv.actual_length = 0;
  1052. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1053. #endif
  1054. if (!maxsize) {
  1055. err("submit_common_message: pipesize for pipe %lx is zero",
  1056. pipe);
  1057. return -1;
  1058. }
  1059. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1060. err("sohci_submit_job failed");
  1061. return -1;
  1062. }
  1063. /* allow more time for a BULK device to react - some are slow */
  1064. #define BULK_TO 5000 /* timeout in milliseconds */
  1065. if (usb_pipetype (pipe) == PIPE_BULK)
  1066. timeout = BULK_TO;
  1067. else
  1068. timeout = 100;
  1069. /* wait for it to complete */
  1070. for (;;) {
  1071. /* check whether the controller is done */
  1072. stat = hc_interrupt();
  1073. if (stat < 0) {
  1074. stat = USB_ST_CRC_ERR;
  1075. break;
  1076. }
  1077. if (stat >= 0 && stat < 0xff) {
  1078. /* 0xff is returned for an SF-interrupt */
  1079. break;
  1080. }
  1081. if (--timeout) {
  1082. wait_ms(1);
  1083. } else {
  1084. err("CTL:TIMEOUT ");
  1085. stat = USB_ST_CRC_ERR;
  1086. break;
  1087. }
  1088. }
  1089. /* we got an Root Hub Status Change interrupt */
  1090. if (got_rhsc) {
  1091. #ifdef DEBUG
  1092. ohci_dump_roothub (&gohci, 1);
  1093. #endif
  1094. got_rhsc = 0;
  1095. /* abuse timeout */
  1096. timeout = rh_check_port_status(&gohci);
  1097. if (timeout >= 0) {
  1098. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1099. /* the called routine adds 1 to the passed value */
  1100. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1101. #endif
  1102. /*
  1103. * XXX
  1104. * This is potentially dangerous because it assumes
  1105. * that only one device is ever plugged in!
  1106. */
  1107. devgone = dev;
  1108. }
  1109. }
  1110. dev->status = stat;
  1111. dev->act_len = transfer_len;
  1112. #ifdef DEBUG
  1113. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1114. #endif
  1115. /* free TDs in urb_priv */
  1116. urb_free_priv (&urb_priv);
  1117. return 0;
  1118. }
  1119. /* submit routines called from usb.c */
  1120. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1121. int transfer_len)
  1122. {
  1123. info("submit_bulk_msg");
  1124. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1125. }
  1126. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1127. int transfer_len, struct devrequest *setup)
  1128. {
  1129. int maxsize = usb_maxpacket(dev, pipe);
  1130. info("submit_control_msg");
  1131. #ifdef DEBUG
  1132. urb_priv.actual_length = 0;
  1133. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1134. #endif
  1135. if (!maxsize) {
  1136. err("submit_control_message: pipesize for pipe %lx is zero",
  1137. pipe);
  1138. return -1;
  1139. }
  1140. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1141. gohci.rh.dev = dev;
  1142. /* root hub - redirect */
  1143. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1144. setup);
  1145. }
  1146. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1147. }
  1148. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1149. int transfer_len, int interval)
  1150. {
  1151. info("submit_int_msg");
  1152. return -1;
  1153. }
  1154. /*-------------------------------------------------------------------------*
  1155. * HC functions
  1156. *-------------------------------------------------------------------------*/
  1157. /* reset the HC and BUS */
  1158. static int hc_reset (ohci_t *ohci)
  1159. {
  1160. int timeout = 30;
  1161. int smm_timeout = 50; /* 0,5 sec */
  1162. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1163. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1164. info("USB HC TakeOver from SMM");
  1165. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1166. wait_ms (10);
  1167. if (--smm_timeout == 0) {
  1168. err("USB HC TakeOver failed!");
  1169. return -1;
  1170. }
  1171. }
  1172. }
  1173. /* Disable HC interrupts */
  1174. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1175. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1176. ohci->slot_name,
  1177. readl (&ohci->regs->control));
  1178. /* Reset USB (needed by some controllers) */
  1179. ohci->hc_control = 0;
  1180. writel (ohci->hc_control, &ohci->regs->control);
  1181. /* HC Reset requires max 10 us delay */
  1182. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1183. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1184. if (--timeout == 0) {
  1185. err("USB HC reset timed out!");
  1186. return -1;
  1187. }
  1188. udelay (1);
  1189. }
  1190. return 0;
  1191. }
  1192. /*-------------------------------------------------------------------------*/
  1193. /* Start an OHCI controller, set the BUS operational
  1194. * enable interrupts
  1195. * connect the virtual root hub */
  1196. static int hc_start (ohci_t * ohci)
  1197. {
  1198. __u32 mask;
  1199. unsigned int fminterval;
  1200. ohci->disabled = 1;
  1201. /* Tell the controller where the control and bulk lists are
  1202. * The lists are empty now. */
  1203. writel (0, &ohci->regs->ed_controlhead);
  1204. writel (0, &ohci->regs->ed_bulkhead);
  1205. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1206. fminterval = 0x2edf;
  1207. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1208. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1209. writel (fminterval, &ohci->regs->fminterval);
  1210. writel (0x628, &ohci->regs->lsthresh);
  1211. /* start controller operations */
  1212. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1213. ohci->disabled = 0;
  1214. writel (ohci->hc_control, &ohci->regs->control);
  1215. /* disable all interrupts */
  1216. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1217. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1218. OHCI_INTR_OC | OHCI_INTR_MIE);
  1219. writel (mask, &ohci->regs->intrdisable);
  1220. /* clear all interrupts */
  1221. mask &= ~OHCI_INTR_MIE;
  1222. writel (mask, &ohci->regs->intrstatus);
  1223. /* Choose the interrupts we care about now - but w/o MIE */
  1224. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1225. writel (mask, &ohci->regs->intrenable);
  1226. #ifdef OHCI_USE_NPS
  1227. /* required for AMD-756 and some Mac platforms */
  1228. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1229. &ohci->regs->roothub.a);
  1230. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1231. #endif /* OHCI_USE_NPS */
  1232. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1233. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1234. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1235. /* connect the virtual root hub */
  1236. ohci->rh.devnum = 0;
  1237. return 0;
  1238. }
  1239. /*-------------------------------------------------------------------------*/
  1240. /* an interrupt happens */
  1241. static int
  1242. hc_interrupt (void)
  1243. {
  1244. ohci_t *ohci = &gohci;
  1245. struct ohci_regs *regs = ohci->regs;
  1246. int ints;
  1247. int stat = -1;
  1248. if ((ohci->hcca->done_head != 0) && !(ohci_cpu_to_le32 (ohci->hcca->done_head) & 0x01)) {
  1249. ints = OHCI_INTR_WDH;
  1250. } else {
  1251. ints = readl (&regs->intrstatus);
  1252. }
  1253. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1254. if (ints & OHCI_INTR_RHSC) {
  1255. got_rhsc = 1;
  1256. }
  1257. if (ints & OHCI_INTR_UE) {
  1258. ohci->disabled++;
  1259. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1260. ohci->slot_name);
  1261. /* e.g. due to PCI Master/Target Abort */
  1262. #ifdef DEBUG
  1263. ohci_dump (ohci, 1);
  1264. #endif
  1265. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1266. /* Make some non-interrupt context restart the controller. */
  1267. /* Count and limit the retries though; either hardware or */
  1268. /* software errors can go forever... */
  1269. hc_reset (ohci);
  1270. return -1;
  1271. }
  1272. if (ints & OHCI_INTR_WDH) {
  1273. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1274. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1275. writel (OHCI_INTR_WDH, &regs->intrenable);
  1276. }
  1277. if (ints & OHCI_INTR_SO) {
  1278. dbg("USB Schedule overrun\n");
  1279. writel (OHCI_INTR_SO, &regs->intrenable);
  1280. stat = -1;
  1281. }
  1282. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1283. if (ints & OHCI_INTR_SF) {
  1284. unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
  1285. writel (OHCI_INTR_SF, &regs->intrdisable);
  1286. if (ohci->ed_rm_list[frame] != NULL)
  1287. writel (OHCI_INTR_SF, &regs->intrenable);
  1288. stat = 0xff;
  1289. }
  1290. writel (ints, &regs->intrstatus);
  1291. return stat;
  1292. }
  1293. /*-------------------------------------------------------------------------*/
  1294. /*-------------------------------------------------------------------------*/
  1295. /* De-allocate all resources.. */
  1296. static void hc_release_ohci (ohci_t *ohci)
  1297. {
  1298. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1299. if (!ohci->disabled)
  1300. hc_reset (ohci);
  1301. }
  1302. /*-------------------------------------------------------------------------*/
  1303. /*
  1304. * low level initalisation routine, called from usb.c
  1305. */
  1306. static char ohci_inited = 0;
  1307. int usb_lowlevel_init(void)
  1308. {
  1309. /* Set the USB Clock */
  1310. *(vu_long *)MPC5XXX_CDM_48_FDC = 0x0001bbbb;
  1311. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00800000;
  1312. /* Activate USB port */
  1313. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00001000;
  1314. memset (&gohci, 0, sizeof (ohci_t));
  1315. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1316. /* align the storage */
  1317. if ((__u32)&ghcca[0] & 0xff) {
  1318. err("HCCA not aligned!!");
  1319. return -1;
  1320. }
  1321. phcca = &ghcca[0];
  1322. info("aligned ghcca %p", phcca);
  1323. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1324. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1325. err("EDs not aligned!!");
  1326. return -1;
  1327. }
  1328. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1329. if ((__u32)gtd & 0x7) {
  1330. err("TDs not aligned!!");
  1331. return -1;
  1332. }
  1333. ptd = gtd;
  1334. gohci.hcca = phcca;
  1335. memset (phcca, 0, sizeof (struct ohci_hcca));
  1336. gohci.disabled = 1;
  1337. gohci.sleeping = 0;
  1338. gohci.irq = -1;
  1339. gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
  1340. gohci.flags = 0;
  1341. gohci.slot_name = "mpc5200";
  1342. if (hc_reset (&gohci) < 0) {
  1343. hc_release_ohci (&gohci);
  1344. return -1;
  1345. }
  1346. if (hc_start (&gohci) < 0) {
  1347. err ("can't start usb-%s", gohci.slot_name);
  1348. hc_release_ohci (&gohci);
  1349. return -1;
  1350. }
  1351. #ifdef DEBUG
  1352. ohci_dump (&gohci, 1);
  1353. #endif
  1354. ohci_inited = 1;
  1355. return 0;
  1356. }
  1357. int usb_lowlevel_stop(void)
  1358. {
  1359. /* this gets called really early - before the controller has */
  1360. /* even been initialized! */
  1361. if (!ohci_inited)
  1362. return 0;
  1363. /* TODO release any interrupts, etc. */
  1364. /* call hc_release_ohci() here ? */
  1365. hc_reset (&gohci);
  1366. return 0;
  1367. }
  1368. #endif /* CONFIG_USB_OHCI */