tx25.c 4.6 KB

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  1. /*
  2. * (C) Copyright 2009 DENX Software Engineering
  3. * Author: John Rigby <jrigby@gmail.com>
  4. *
  5. * Based on imx27lite.c:
  6. * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
  7. * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
  8. * And:
  9. * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. *
  26. */
  27. #include <common.h>
  28. #include <asm/io.h>
  29. #include <asm/arch/imx-regs.h>
  30. #include <asm/arch/imx25-pinmux.h>
  31. #include <asm/gpio.h>
  32. #include <asm/arch/sys_proto.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifdef CONFIG_FEC_MXC
  35. void tx25_fec_init(void)
  36. {
  37. struct iomuxc_mux_ctl *muxctl;
  38. struct iomuxc_pad_ctl *padctl;
  39. u32 val;
  40. u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
  41. struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
  42. struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
  43. u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
  44. debug("tx25_fec_init\n");
  45. /*
  46. * fec pin init is generic
  47. */
  48. mx25_fec_init_pins();
  49. /*
  50. * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
  51. *
  52. * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
  53. * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
  54. */
  55. muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
  56. padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
  57. writel(gpio_mux_mode, &muxctl->pad_d13);
  58. writel(gpio_mux_mode, &muxctl->pad_d11);
  59. writel(0x0, &padctl->pad_d13);
  60. writel(0x0, &padctl->pad_d11);
  61. /* drop PHY power and assert reset (low) */
  62. val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9));
  63. writel(val, &gpio4->gpio_dr);
  64. val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9);
  65. writel(val, &gpio4->gpio_dir);
  66. mdelay(5);
  67. debug("resetting phy\n");
  68. /* turn on PHY power leaving reset asserted */
  69. val = readl(&gpio4->gpio_dr) | 1 << 9;
  70. writel(val, &gpio4->gpio_dr);
  71. mdelay(10);
  72. /*
  73. * Setup some strapping pins that are latched by the PHY
  74. * as reset goes high.
  75. *
  76. * Set PHY mode to 111
  77. * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
  78. * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
  79. * mode2 is tied high so nothing to do
  80. *
  81. * Turn on RMII mode
  82. * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
  83. */
  84. /*
  85. * save three current mux modes and set each to gpio mode
  86. */
  87. saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
  88. saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
  89. saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
  90. writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
  91. writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
  92. writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
  93. /*
  94. * set each to 1 and make each an output
  95. */
  96. val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12);
  97. writel(val, &gpio3->gpio_dr);
  98. val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12);
  99. writel(val, &gpio3->gpio_dir);
  100. mdelay(22); /* this value came from RedBoot */
  101. /*
  102. * deassert PHY reset
  103. */
  104. val = readl(&gpio4->gpio_dr) | 1 << 7;
  105. writel(val, &gpio4->gpio_dr);
  106. writel(val, &gpio4->gpio_dr);
  107. mdelay(5);
  108. /*
  109. * set FEC pins back
  110. */
  111. writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
  112. writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
  113. writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
  114. }
  115. #else
  116. #define tx25_fec_init()
  117. #endif
  118. int board_init()
  119. {
  120. #ifdef CONFIG_MXC_UART
  121. mx25_uart1_init_pins();
  122. #endif
  123. /* board id for linux */
  124. gd->bd->bi_arch_number = MACH_TYPE_TX25;
  125. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  126. return 0;
  127. }
  128. int board_late_init(void)
  129. {
  130. tx25_fec_init();
  131. return 0;
  132. }
  133. int dram_init(void)
  134. {
  135. /* dram_init must store complete ramsize in gd->ram_size */
  136. gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
  137. PHYS_SDRAM_1_SIZE);
  138. return 0;
  139. }
  140. void dram_init_banksize(void)
  141. {
  142. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  143. gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
  144. PHYS_SDRAM_1_SIZE);
  145. #if CONFIG_NR_DRAM_BANKS > 1
  146. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  147. gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
  148. PHYS_SDRAM_2_SIZE);
  149. #else
  150. #endif
  151. }
  152. int checkboard(void)
  153. {
  154. printf("KARO TX25\n");
  155. return 0;
  156. }