quantum.c 6.5 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <mpc8xx.h>
  25. #include "fpga.h"
  26. /* ------------------------------------------------------------------------- */
  27. static long int dram_size (long int, long int *, long int);
  28. unsigned long flash_init (void);
  29. /* ------------------------------------------------------------------------- */
  30. #define _NOT_USED_ 0xFFFFCC25
  31. const uint sdram_table[] = {
  32. /*
  33. * Single Read. (Offset 00h in UPMA RAM)
  34. */
  35. 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
  36. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  37. /*
  38. * Burst Read. (Offset 08h in UPMA RAM)
  39. */
  40. 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
  41. 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
  42. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  43. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  44. /*
  45. * Single Write. (Offset 18h in UPMA RAM)
  46. */
  47. 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
  48. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  49. /*
  50. * Burst Write. (Offset 20h in UPMA RAM)
  51. */
  52. 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
  53. 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
  54. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  55. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  56. /*
  57. * Refresh. (Offset 30h in UPMA RAM)
  58. * (Initialization code at 0x36)
  59. */
  60. 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
  61. _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
  62. 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
  63. /*
  64. * Exception. (Offset 3Ch in UPMA RAM)
  65. */
  66. 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
  67. };
  68. /* ------------------------------------------------------------------------- */
  69. /*
  70. * Check Board Identity:
  71. */
  72. int checkboard (void)
  73. {
  74. char *s = getenv ("serial#");
  75. puts ("Board QUANTUM, Serial No: ");
  76. for (; s && *s; ++s) {
  77. if (*s == ' ')
  78. break;
  79. putc (*s);
  80. }
  81. putc ('\n');
  82. return (0); /* success */
  83. }
  84. /* ------------------------------------------------------------------------- */
  85. long int initdram (int board_type)
  86. {
  87. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  88. volatile memctl8xx_t *memctl = &immap->im_memctl;
  89. long int size9;
  90. upmconfig (UPMA, (uint *) sdram_table,
  91. sizeof (sdram_table) / sizeof (uint));
  92. /* Refresh clock prescalar */
  93. memctl->memc_mptpr = CFG_MPTPR;
  94. memctl->memc_mar = 0x00000088;
  95. /* Map controller banks 1 to the SDRAM bank */
  96. memctl->memc_or1 = CFG_OR1_PRELIM;
  97. memctl->memc_br1 = CFG_BR1_PRELIM;
  98. memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
  99. udelay (200);
  100. /* perform SDRAM initializsation sequence */
  101. memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */
  102. udelay (1);
  103. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  104. udelay (1000);
  105. /* Check Bank 0 Memory Size,
  106. * 9 column mode
  107. */
  108. size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
  109. SDRAM_MAX_SIZE);
  110. /*
  111. * Final mapping:
  112. */
  113. memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
  114. udelay (1000);
  115. return (size9);
  116. }
  117. /* ------------------------------------------------------------------------- */
  118. /*
  119. * Check memory range for valid RAM. A simple memory test determines
  120. * the actually available RAM size between addresses `base' and
  121. * `base + maxsize'. Some (not all) hardware errors are detected:
  122. * - short between address lines
  123. * - short between data lines
  124. */
  125. static long int dram_size (long int mamr_value, long int *base,
  126. long int maxsize)
  127. {
  128. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  129. volatile memctl8xx_t *memctl = &immap->im_memctl;
  130. volatile ulong *addr;
  131. ulong cnt, val, size;
  132. ulong save[32]; /* to make test non-destructive */
  133. unsigned char i = 0;
  134. memctl->memc_mamr = mamr_value;
  135. for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
  136. addr = base + cnt; /* pointer arith! */
  137. save[i++] = *addr;
  138. *addr = ~cnt;
  139. }
  140. /* write 0 to base address */
  141. addr = base;
  142. save[i] = *addr;
  143. *addr = 0;
  144. /* check at base address */
  145. if ((val = *addr) != 0) {
  146. /* Restore the original data before leaving the function.
  147. */
  148. *addr = save[i];
  149. for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
  150. addr = (volatile ulong *) base + cnt;
  151. *addr = save[--i];
  152. }
  153. return (0);
  154. }
  155. for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
  156. addr = base + cnt; /* pointer arith! */
  157. val = *addr;
  158. *addr = save[--i];
  159. if (val != (~cnt)) {
  160. size = cnt * sizeof (long);
  161. /* Restore the original data before returning
  162. */
  163. for (cnt <<= 1; cnt <= maxsize / sizeof (long);
  164. cnt <<= 1) {
  165. addr = (volatile ulong *) base + cnt;
  166. *addr = save[--i];
  167. }
  168. return (size);
  169. }
  170. }
  171. return (maxsize);
  172. }
  173. /*
  174. * Miscellaneous intialization
  175. */
  176. int misc_init_r (void)
  177. {
  178. char *fpga_data_str = getenv ("fpgadata");
  179. char *fpga_size_str = getenv ("fpgasize");
  180. void *fpga_data;
  181. int fpga_size;
  182. int status;
  183. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  184. volatile memctl8xx_t *memctl = &immap->im_memctl;
  185. int flash_size;
  186. /* Remap FLASH according to real size */
  187. flash_size = flash_init ();
  188. memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
  189. memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
  190. if (fpga_data_str && fpga_size_str) {
  191. fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
  192. fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
  193. status = fpga_boot (fpga_data, fpga_size);
  194. if (status != 0) {
  195. printf ("\nFPGA: Booting failed ");
  196. switch (status) {
  197. case ERROR_FPGA_PRG_INIT_LOW:
  198. printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
  199. break;
  200. case ERROR_FPGA_PRG_INIT_HIGH:
  201. printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
  202. break;
  203. case ERROR_FPGA_PRG_DONE:
  204. printf ("(Timeout: DONE not high after programming FPGA)\n ");
  205. break;
  206. }
  207. }
  208. }
  209. return 0;
  210. }