chip_config.c 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. /*
  2. * (C) Copyright 2009
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h>
  25. #include <asm/ppc4xx_config.h>
  26. /* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
  27. struct ppc4xx_config ppc4xx_config_val[] = {
  28. {
  29. "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
  30. {
  31. 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
  32. 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  33. }
  34. },
  35. {
  36. "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
  37. {
  38. 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
  39. 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  40. }
  41. },
  42. {
  43. "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66",
  44. {
  45. 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
  46. 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  47. }
  48. },
  49. {
  50. "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
  51. {
  52. 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
  53. 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  54. }
  55. },
  56. {
  57. "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
  58. {
  59. 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
  60. 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  61. }
  62. },
  63. {
  64. "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
  65. {
  66. 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
  67. 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  68. }
  69. },
  70. {
  71. "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
  72. {
  73. 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
  74. 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  75. }
  76. },
  77. {
  78. "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
  79. {
  80. 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
  81. 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  82. }
  83. },
  84. {
  85. "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
  86. {
  87. 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
  88. 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  89. }
  90. },
  91. };
  92. int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);