km82xx.c 15 KB

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  1. /*
  2. * (C) Copyright 2007 - 2008
  3. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <mpc8260.h>
  25. #include <ioports.h>
  26. #include <malloc.h>
  27. #include <asm/io.h>
  28. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  29. #include <libfdt.h>
  30. #endif
  31. #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
  32. #include <i2c.h>
  33. #endif
  34. #include "../common/common.h"
  35. /*
  36. * I/O Port configuration table
  37. *
  38. * if conf is 1, then that port pin will be configured at boot time
  39. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  40. */
  41. const iop_conf_t iop_conf_tab[4][32] = {
  42. /* Port A */
  43. { /* conf ppar psor pdir podr pdat */
  44. { 0, 0, 0, 0, 0, 0 }, /* PA31 */
  45. { 0, 0, 0, 0, 0, 0 }, /* PA30 */
  46. { 0, 0, 0, 0, 0, 0 }, /* PA29 */
  47. { 0, 0, 0, 0, 0, 0 }, /* PA28 */
  48. { 0, 0, 0, 0, 0, 0 }, /* PA27 */
  49. { 0, 0, 0, 0, 0, 0 }, /* PA26 */
  50. { 0, 0, 0, 0, 0, 0 }, /* PA25 */
  51. { 0, 0, 0, 0, 0, 0 }, /* PA24 */
  52. { 0, 0, 0, 0, 0, 0 }, /* PA23 */
  53. { 0, 0, 0, 0, 0, 0 }, /* PA22 */
  54. { 0, 0, 0, 0, 0, 0 }, /* PA21 */
  55. { 0, 0, 0, 0, 0, 0 }, /* PA20 */
  56. { 0, 0, 0, 0, 0, 0 }, /* PA19 */
  57. { 0, 0, 0, 0, 0, 0 }, /* PA18 */
  58. { 0, 0, 0, 0, 0, 0 }, /* PA17 */
  59. { 0, 0, 0, 0, 0, 0 }, /* PA16 */
  60. { 0, 0, 0, 0, 0, 0 }, /* PA15 */
  61. { 0, 0, 0, 0, 0, 0 }, /* PA14 */
  62. { 0, 0, 0, 0, 0, 0 }, /* PA13 */
  63. { 0, 0, 0, 0, 0, 0 }, /* PA12 */
  64. { 0, 0, 0, 0, 0, 0 }, /* PA11 */
  65. { 0, 0, 0, 0, 0, 0 }, /* PA10 */
  66. { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */
  67. { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */
  68. { 0, 0, 0, 0, 0, 0 }, /* PA7 */
  69. { 0, 0, 0, 0, 0, 0 }, /* PA6 */
  70. { 0, 0, 0, 0, 0, 0 }, /* PA5 */
  71. { 0, 0, 0, 0, 0, 0 }, /* PA4 */
  72. { 0, 0, 0, 0, 0, 0 }, /* PA3 */
  73. { 0, 0, 0, 0, 0, 0 }, /* PA2 */
  74. { 0, 0, 0, 0, 0, 0 }, /* PA1 */
  75. { 0, 0, 0, 0, 0, 0 } /* PA0 */
  76. },
  77. /* Port B */
  78. { /* conf ppar psor pdir podr pdat */
  79. { 0, 0, 0, 0, 0, 0 }, /* PB31 */
  80. { 0, 0, 0, 0, 0, 0 }, /* PB30 */
  81. { 0, 0, 0, 0, 0, 0 }, /* PB29 */
  82. { 0, 0, 0, 0, 0, 0 }, /* PB28 */
  83. { 0, 0, 0, 0, 0, 0 }, /* PB27 */
  84. { 0, 0, 0, 0, 0, 0 }, /* PB26 */
  85. { 0, 0, 0, 0, 0, 0 }, /* PB25 */
  86. { 0, 0, 0, 0, 0, 0 }, /* PB24 */
  87. { 0, 0, 0, 0, 0, 0 }, /* PB23 */
  88. { 0, 0, 0, 0, 0, 0 }, /* PB22 */
  89. { 0, 0, 0, 0, 0, 0 }, /* PB21 */
  90. { 0, 0, 0, 0, 0, 0 }, /* PB20 */
  91. { 0, 0, 0, 0, 0, 0 }, /* PB19 */
  92. { 0, 0, 0, 0, 0, 0 }, /* PB18 */
  93. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  94. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  95. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  96. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  97. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  98. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  99. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  100. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  101. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  102. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  103. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  104. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  105. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  106. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  107. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  108. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  109. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  110. { 0, 0, 0, 0, 0, 0 } /* non-existent */
  111. },
  112. /* Port C */
  113. { /* conf ppar psor pdir podr pdat */
  114. { 0, 0, 0, 0, 0, 0 }, /* PC31 */
  115. { 0, 0, 0, 0, 0, 0 }, /* PC30 */
  116. { 0, 0, 0, 0, 0, 0 }, /* PC29 */
  117. { 0, 0, 0, 0, 0, 0 }, /* PC28 */
  118. { 0, 0, 0, 0, 0, 0 }, /* PC27 */
  119. { 0, 0, 0, 0, 0, 0 }, /* PC26 */
  120. { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */
  121. { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */
  122. { 0, 0, 0, 0, 0, 0 }, /* PC23 */
  123. { 0, 0, 0, 0, 0, 0 }, /* PC22 */
  124. { 0, 0, 0, 0, 0, 0 }, /* PC21 */
  125. { 0, 0, 0, 0, 0, 0 }, /* PC20 */
  126. { 0, 0, 0, 0, 0, 0 }, /* PC19 */
  127. { 0, 0, 0, 0, 0, 0 }, /* PC18 */
  128. { 0, 0, 0, 0, 0, 0 }, /* PC17 */
  129. { 0, 0, 0, 0, 0, 0 }, /* PC16 */
  130. { 0, 0, 0, 0, 0, 0 }, /* PC15 */
  131. { 0, 0, 0, 0, 0, 0 }, /* PC14 */
  132. { 0, 0, 0, 0, 0, 0 }, /* PC13 */
  133. { 0, 0, 0, 0, 0, 0 }, /* PC12 */
  134. { 0, 0, 0, 0, 0, 0 }, /* PC11 */
  135. { 0, 0, 0, 0, 0, 0 }, /* PC10 */
  136. { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */
  137. { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */
  138. { 0, 0, 0, 0, 0, 0 }, /* PC7 */
  139. { 0, 0, 0, 0, 0, 0 }, /* PC6 */
  140. { 0, 0, 0, 0, 0, 0 }, /* PC5 */
  141. { 0, 0, 0, 0, 0, 0 }, /* PC4 */
  142. { 0, 0, 0, 0, 0, 0 }, /* PC3 */
  143. { 0, 0, 0, 0, 0, 0 }, /* PC2 */
  144. { 0, 0, 0, 0, 0, 0 }, /* PC1 */
  145. { 0, 0, 0, 0, 0, 0 }, /* PC0 */
  146. },
  147. /* Port D */
  148. { /* conf ppar psor pdir podr pdat */
  149. { 0, 0, 0, 0, 0, 0 }, /* PD31 */
  150. { 0, 0, 0, 0, 0, 0 }, /* PD30 */
  151. { 0, 0, 0, 0, 0, 0 }, /* PD29 */
  152. { 0, 0, 0, 0, 0, 0 }, /* PD28 */
  153. { 0, 0, 0, 0, 0, 0 }, /* PD27 */
  154. { 0, 0, 0, 0, 0, 0 }, /* PD26 */
  155. { 0, 0, 0, 0, 0, 0 }, /* PD25 */
  156. { 0, 0, 0, 0, 0, 0 }, /* PD24 */
  157. { 0, 0, 0, 0, 0, 0 }, /* PD23 */
  158. { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */
  159. { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */
  160. { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */
  161. { 0, 0, 0, 0, 0, 0 }, /* PD19 */
  162. { 0, 0, 0, 0, 0, 0 }, /* PD18 */
  163. { 0, 0, 0, 0, 0, 0 }, /* PD17 */
  164. { 0, 0, 0, 0, 0, 0 }, /* PD16 */
  165. #if defined(CONFIG_HARD_I2C)
  166. { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
  167. { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
  168. #else
  169. { 1, 0, 0, 0, 1, 1 }, /* PD15 */
  170. { 1, 0, 0, 1, 1, 1 }, /* PD14 */
  171. #endif
  172. { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  173. { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  174. { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  175. { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  176. { 0, 0, 0, 0, 0, 0 }, /* PD9 */
  177. { 0, 0, 0, 0, 0, 0 }, /* PD8 */
  178. { 0, 0, 0, 0, 0, 0 }, /* PD7 */
  179. { 0, 0, 0, 0, 0, 0 }, /* PD6 */
  180. { 0, 0, 0, 0, 0, 0 }, /* PD5 */
  181. { 0, 0, 0, 0, 0, 0 }, /* PD4 */
  182. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  183. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  184. { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  185. { 0, 0, 0, 0, 0, 0 } /* non-existent */
  186. }
  187. };
  188. /*
  189. * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
  190. *
  191. * This routine performs standard 8260 initialization sequence
  192. * and calculates the available memory size. It may be called
  193. * several times to try different SDRAM configurations on both
  194. * 60x and local buses.
  195. */
  196. static long int try_init(memctl8260_t *memctl, ulong sdmr,
  197. ulong orx, uchar *base)
  198. {
  199. uchar c = 0xff;
  200. ulong maxsize, size;
  201. int i;
  202. /*
  203. * We must be able to test a location outsize the maximum legal size
  204. * to find out THAT we are outside; but this address still has to be
  205. * mapped by the controller. That means, that the initial mapping has
  206. * to be (at least) twice as large as the maximum expected size.
  207. */
  208. maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
  209. out_be32(&memctl->memc_or1, orx);
  210. /*
  211. * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
  212. *
  213. * "At system reset, initialization software must set up the
  214. * programmable parameters in the memory controller banks registers
  215. * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
  216. * system software should execute the following initialization sequence
  217. * for each SDRAM device.
  218. *
  219. * 1. Issue a PRECHARGE-ALL-BANKS command
  220. * 2. Issue eight CBR REFRESH commands
  221. * 3. Issue a MODE-SET command to initialize the mode register
  222. *
  223. * The initial commands are executed by setting P/LSDMR[OP] and
  224. * accessing the SDRAM with a single-byte transaction."
  225. *
  226. * The appropriate BRx/ORx registers have already been set when we
  227. * get here. The SDRAM can be accessed at the address
  228. * CONFIG_SYS_SDRAM_BASE.
  229. */
  230. out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
  231. out_8(base, c);
  232. out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
  233. for (i = 0; i < 8; i++)
  234. out_8(base, c);
  235. out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
  236. /* setting MR on address lines */
  237. out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
  238. out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
  239. out_8(base, c);
  240. size = get_ram_size((long *)base, maxsize);
  241. out_be32(&memctl->memc_or1, orx | ~(size - 1));
  242. return size;
  243. }
  244. #ifdef CONFIG_SYS_SDRAM_LIST
  245. /*
  246. * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
  247. * configurations therein (should be from high to lower) to find the
  248. * one actually matching the current configuration.
  249. * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
  250. * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
  251. * (defined as the initialization value for the array of struct sdram_conf_s)
  252. * will then be ORed with such base values.
  253. */
  254. struct sdram_conf_s {
  255. ulong size;
  256. int or1;
  257. int psdmr;
  258. };
  259. static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
  260. static long probe_sdram(memctl8260_t *memctl)
  261. {
  262. int n = 0;
  263. long psize = 0;
  264. for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
  265. psize = try_init(memctl,
  266. CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
  267. CONFIG_SYS_OR1 | sdram_conf[n].or1,
  268. (uchar *) CONFIG_SYS_SDRAM_BASE);
  269. debug("Probing %ld bytes returned %ld\n",
  270. sdram_conf[n].size, psize);
  271. if (psize == sdram_conf[n].size)
  272. break;
  273. }
  274. return psize;
  275. }
  276. #else /* CONFIG_SYS_SDRAM_LIST */
  277. static long probe_sdram(memctl8260_t *memctl)
  278. {
  279. return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
  280. (uchar *) CONFIG_SYS_SDRAM_BASE);
  281. }
  282. #endif /* CONFIG_SYS_SDRAM_LIST */
  283. phys_size_t initdram(int board_type)
  284. {
  285. immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  286. memctl8260_t *memctl = &immap->im_memctl;
  287. long psize;
  288. out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
  289. out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
  290. #ifndef CONFIG_SYS_RAMBOOT
  291. /* 60x SDRAM setup:
  292. */
  293. psize = probe_sdram(memctl);
  294. #endif /* CONFIG_SYS_RAMBOOT */
  295. icache_enable();
  296. return psize;
  297. }
  298. int checkboard(void)
  299. {
  300. #if defined(CONFIG_MGCOGE)
  301. puts("Board: Keymile mgcoge");
  302. #else
  303. puts("Board: Keymile mgcoge3ne");
  304. #endif
  305. if (ethernet_present())
  306. puts(" with PIGGY.");
  307. puts("\n");
  308. return 0;
  309. }
  310. int last_stage_init(void)
  311. {
  312. struct bfticu_iomap *base =
  313. (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
  314. u8 dip_switch;
  315. dip_switch = in_8(&base->mswitch);
  316. dip_switch &= BFTICU_DIPSWITCH_MASK;
  317. /* dip switch 'full reset' or 'db erase' */
  318. if (dip_switch & 0x1 || dip_switch & 0x2) {
  319. /* start bootloader */
  320. puts("DIP: Enabled\n");
  321. setenv("actual_bank", "0");
  322. }
  323. set_km_env();
  324. return 0;
  325. }
  326. #ifdef CONFIG_MGCOGE3NE
  327. static void set_pin(int state, unsigned long mask);
  328. /*
  329. * For mgcoge3ne boards, the mgcoge3un control is controlled from
  330. * a GPIO line on the PPC CPU. If bobcatreset is set the line
  331. * will toggle once what forces the mgocge3un part to restart
  332. * immediately.
  333. */
  334. void handle_mgcoge3un_reset(void)
  335. {
  336. char *bobcatreset = getenv("bobcatreset");
  337. if (bobcatreset) {
  338. if (strcmp(bobcatreset, "true") == 0) {
  339. puts("Forcing bobcat reset\n");
  340. set_pin(0, 0x00000004); /* clear PD29 to reset arm */
  341. udelay(1000);
  342. set_pin(1, 0x00000004);
  343. } else
  344. set_pin(1, 0x00000004); /* set PD29 to not reset arm */
  345. }
  346. }
  347. #endif
  348. int ethernet_present(void)
  349. {
  350. struct km_bec_fpga *base =
  351. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  352. return in_8(&base->bprth) & PIGGY_PRESENT;
  353. }
  354. /*
  355. * Early board initalization.
  356. */
  357. int board_early_init_r(void)
  358. {
  359. struct km_bec_fpga *base =
  360. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  361. /* setup the UPIOx */
  362. /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
  363. out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
  364. /* SCC4 enable, halfduplex, FCC1 powerdown */
  365. out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
  366. H_OPORTS_FCC1_PW_DWN));
  367. #ifdef CONFIG_MGCOGE3NE
  368. handle_mgcoge3un_reset();
  369. #endif
  370. return 0;
  371. }
  372. int hush_init_var(void)
  373. {
  374. ivm_read_eeprom();
  375. return 0;
  376. }
  377. #define SDA_MASK 0x00010000
  378. #define SCL_MASK 0x00020000
  379. static void set_pin(int state, unsigned long mask)
  380. {
  381. ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
  382. if (state)
  383. setbits_be32(&iop->pdat, mask);
  384. else
  385. clrbits_be32(&iop->pdat, mask);
  386. setbits_be32(&iop->pdir, mask);
  387. }
  388. static int get_pin(unsigned long mask)
  389. {
  390. ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
  391. clrbits_be32(&iop->pdir, mask);
  392. return 0 != (in_be32(&iop->pdat) & mask);
  393. }
  394. void set_sda(int state)
  395. {
  396. set_pin(state, SDA_MASK);
  397. }
  398. void set_scl(int state)
  399. {
  400. set_pin(state, SCL_MASK);
  401. }
  402. int get_sda(void)
  403. {
  404. return get_pin(SDA_MASK);
  405. }
  406. int get_scl(void)
  407. {
  408. return get_pin(SCL_MASK);
  409. }
  410. #if defined(CONFIG_HARD_I2C)
  411. static void setports(int gpio)
  412. {
  413. ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
  414. if (gpio) {
  415. clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
  416. clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
  417. } else {
  418. setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
  419. clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
  420. setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
  421. }
  422. }
  423. #endif
  424. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  425. void ft_board_setup(void *blob, bd_t *bd)
  426. {
  427. ft_cpu_setup(blob, bd);
  428. }
  429. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */