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uboot-vybrid_pu...
/
arch
/
arm
/
include
/
asm
/
arch-u8500
/
hardware.h

hardware.h 3.3 KB
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  1. /*
    2. 

  2.  * Copyright (C) ST-Ericsson SA 2009
    3. 

  3.  *
    4. 

  4.  * See file CREDITS for list of people who contributed to this
    5. 

  5.  * project.
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or
    8. 

  8.  * modify it under the terms of the GNU General Public License as
    9. 

  9.  * published by the Free Software Foundation; either version 2 of
    10. 

  10.  * the License, or (at your option) any later version.
    11. 

  11.  *
    12. 

  12.  * This program is distributed in the hope that it will be useful,
    13. 

  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    14. 

  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    15. 

  15.  * GNU General Public License for more details.
    16. 

  16.  *
    17. 

  17.  * You should have received a copy of the GNU General Public License
    18. 

  18.  * along with this program; if not, write to the Free Software
    19. 

  19.  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
    20. 

  20.  * MA 02110-1301 USA
    21. 

  21.  */
    22. 

  22. 

  23. #ifndef __ASM_ARCH_HARDWARE_H
    24. 

  24. #define __ASM_ARCH_HARDWARE_H
    25. 

  25. 

  26. /* Peripheral clusters */
    27. 

  27. 

  28. #define U8500_PER3_BASE		0x80000000
    29. 

  29. #define U8500_PER2_BASE		0x80110000
    30. 

  30. #define U8500_PER1_BASE		0x80120000
    31. 

  31. #define U8500_PER4_BASE		0x80150000
    32. 

  32. 

  33. #define U8500_PER6_BASE		0xa03c0000
    34. 

  34. #define U8500_PER7_BASE		0xa03d0000
    35. 

  35. #define U8500_PER5_BASE		0xa03e0000
    36. 

  36. 

  37. /* GPIO */
    38. 

  38. 

  39. #define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
    40. 

  40. #define U8500_GPIO1_BASE	(U8500_PER1_BASE + 0xE000 + 0x80)
    41. 

  41. 

  42. #define U8500_GPIO2_BASE	(U8500_PER3_BASE + 0xE000)
    43. 

  43. #define U8500_GPIO3_BASE	(U8500_PER3_BASE + 0xE000 + 0x80)
    44. 

  44. #define U8500_GPIO4_BASE	(U8500_PER3_BASE + 0xE000 + 0x100)
    45. 

  45. #define U8500_GPIO5_BASE	(U8500_PER3_BASE + 0xE000 + 0x180)
    46. 

  46. 

  47. #define U8500_GPIO6_BASE	(U8500_PER2_BASE + 0xE000)
    48. 

  48. #define U8500_GPIO7_BASE	(U8500_PER2_BASE + 0xE000 + 0x80)
    49. 

  49. 

  50. #define U8500_GPIO8_BASE	(U8500_PER5_BASE + 0x1E000)
    51. 

  51. 

  52. /* Per7 */
    53. 

  53. #define U8500_CLKRST7_BASE	(U8500_PER7_BASE + 0xf000)
    54. 

  54. 

  55. /* Per6 */
    56. 

  56. #define U8500_MTU0_BASE_V1	(U8500_PER6_BASE + 0x6000)
    57. 

  57. #define U8500_MTU1_BASE_V1	(U8500_PER6_BASE + 0x7000)
    58. 

  58. #define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)
    59. 

  59. 

  60. /* Per5 */
    61. 

  61. #define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)
    62. 

  62. 

  63. /* Per4 */
    64. 

  64. #define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
    65. 

  65. #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
    66. 

  66. 

  67. /* Per3 */
    68. 

  68. #define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
    69. 

  69. #define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)
    70. 

  70. 

  71. /* Per2 */
    72. 

  72. #define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)
    73. 

  73. 

  74. /* Per1 */
    75. 

  75. #define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
    76. 

  76. #define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
    77. 

  77. #define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)
    78. 

  78. 

  79. /* Last page of Boot ROM */
    80. 

  80. #define U8500_BOOTROM_BASE      0x90000000
    81. 

  81. #define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
    82. 

  82. #define U8500_ASIC_ID_LOC_V2    (U8500_BOOTROM_BASE + 0x1DBF4)
    83. 

  83. 

  84. /* AB8500 specifics */
    85. 

  85. 

  86. /* address bank */
    87. 

  87. #define AB8500_REGU_CTRL2	0x0004
    88. 

  88. #define AB8500_MISC		0x0010
    89. 

  89. 

  90. /* registers */
    91. 

  91. #define AB8500_REGU_VRF1VAUX3_REGU_REG	0x040A
    92. 

  92. #define AB8500_REGU_VRF1VAUX3_SEL_REG	0x0421
    93. 

  93. #define AB8500_REV_REG			0x1080
    94. 

  94. 

  95. #define AB8500_GPIO_SEL2_REG	0x1001
    96. 

  96. #define AB8500_GPIO_DIR2_REG	0x1011
    97. 

  97. #define AB8500_GPIO_DIR4_REG	0x1013
    98. 

  98. #define AB8500_GPIO_SEL4_REG	0x1003
    99. 

  99. #define AB8500_GPIO_OUT2_REG	0x1021
    100. 

  100. #define AB8500_GPIO_OUT4_REG	0x1023
    101. 

  101. 

  102. #define LDO_VAUX3_ENABLE_MASK	0x3
    103. 

  103. #define LDO_VAUX3_ENABLE_VAL	0x1
    104. 

  104. #define LDO_VAUX3_SEL_MASK	0xf
    105. 

  105. #define LDO_VAUX3_SEL_2V9	0xd
    106. 

  106. #define LDO_VAUX3_V2_SEL_MASK	0x7
    107. 

  107. #define LDO_VAUX3_V2_SEL_2V91	0x7
    108. 

  108. 

  109. 

  110. #endif /* __ASM_ARCH_HARDWARE_H */
    111.