cache.c 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950
  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/cache.h>
  25. void flush_cache (ulong start_addr, ulong size)
  26. {
  27. #ifndef CONFIG_5xx
  28. ulong addr, end_addr = start_addr + size;
  29. if (CFG_CACHELINE_SIZE) {
  30. addr = start_addr & (CFG_CACHELINE_SIZE - 1);
  31. for (addr = start_addr;
  32. addr < end_addr;
  33. addr += CFG_CACHELINE_SIZE) {
  34. asm ("dcbst 0,%0": :"r" (addr));
  35. }
  36. asm ("sync"); /* Wait for all dcbst to complete on bus */
  37. for (addr = start_addr;
  38. addr < end_addr;
  39. addr += CFG_CACHELINE_SIZE) {
  40. asm ("icbi 0,%0": :"r" (addr));
  41. }
  42. }
  43. asm ("sync"); /* Always flush prefetch queue in any case */
  44. asm ("isync");
  45. #endif
  46. }