M5235EVB.h 7.5 KB

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  1. /*
  2. * Configuation settings for the Freescale MCF5329 FireEngine board.
  3. *
  4. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * board/config.h - configuration options, board specific
  27. */
  28. #ifndef _M5235EVB_H
  29. #define _M5235EVB_H
  30. /*
  31. * High Level Configuration Options
  32. * (easy to change)
  33. */
  34. #define CONFIG_MCF523x /* define processor family */
  35. #define CONFIG_M5235 /* define processor type */
  36. #undef DEBUG
  37. #define CONFIG_MCFUART
  38. #define CFG_UART_PORT (0)
  39. #define CONFIG_BAUDRATE 115200
  40. #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  41. #undef CONFIG_WATCHDOG
  42. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  43. /*
  44. * BOOTP options
  45. */
  46. #define CONFIG_BOOTP_BOOTFILESIZE
  47. #define CONFIG_BOOTP_BOOTPATH
  48. #define CONFIG_BOOTP_GATEWAY
  49. #define CONFIG_BOOTP_HOSTNAME
  50. /* Command line configuration */
  51. #include <config_cmd_default.h>
  52. #define CONFIG_CMD_BOOTD
  53. #define CONFIG_CMD_CACHE
  54. #define CONFIG_CMD_DHCP
  55. #define CONFIG_CMD_ELF
  56. #define CONFIG_CMD_FLASH
  57. #define CONFIG_CMD_I2C
  58. #define CONFIG_CMD_MEMORY
  59. #define CONFIG_CMD_MISC
  60. #define CONFIG_CMD_MII
  61. #define CONFIG_CMD_NET
  62. #define CONFIG_CMD_PCI
  63. #define CONFIG_CMD_PING
  64. #define CONFIG_CMD_REGINFO
  65. #undef CONFIG_CMD_LOADB
  66. #undef CONFIG_CMD_LOADS
  67. #define CONFIG_MCFFEC
  68. #ifdef CONFIG_MCFFEC
  69. # define CONFIG_NET_MULTI 1
  70. # define CONFIG_MII 1
  71. # define CFG_DISCOVER_PHY
  72. # define CFG_RX_ETH_BUFFER 8
  73. # define CFG_FAULT_ECHO_LINK_DOWN
  74. # define CFG_FEC0_PINMUX 0
  75. # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
  76. # define MCFFEC_TOUT_LOOP 50000
  77. /* If CFG_DISCOVER_PHY is not defined - hardcoded */
  78. # ifndef CFG_DISCOVER_PHY
  79. # define FECDUPLEX FULL
  80. # define FECSPEED _100BASET
  81. # else
  82. # ifndef CFG_FAULT_ECHO_LINK_DOWN
  83. # define CFG_FAULT_ECHO_LINK_DOWN
  84. # endif
  85. # endif /* CFG_DISCOVER_PHY */
  86. #endif
  87. /* Timer */
  88. #define CONFIG_MCFTMR
  89. #undef CONFIG_MCFPIT
  90. /* I2C */
  91. #define CONFIG_FSL_I2C
  92. #define CONFIG_HARD_I2C /* I2C with hw support */
  93. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  94. #define CFG_I2C_SPEED 80000
  95. #define CFG_I2C_SLAVE 0x7F
  96. #define CFG_I2C_OFFSET 0x00000300
  97. #define CFG_IMMR CFG_MBAR
  98. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  99. #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
  100. #define CONFIG_BOOTFILE "u-boot.bin"
  101. #ifdef CONFIG_MCFFEC
  102. # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
  103. # define CONFIG_IPADDR 192.162.1.2
  104. # define CONFIG_NETMASK 255.255.255.0
  105. # define CONFIG_SERVERIP 192.162.1.1
  106. # define CONFIG_GATEWAYIP 192.162.1.1
  107. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  108. #endif /* FEC_ENET */
  109. #define CONFIG_HOSTNAME M5235EVB
  110. #define CONFIG_EXTRA_ENV_SETTINGS \
  111. "netdev=eth0\0" \
  112. "loadaddr=10000\0" \
  113. "u-boot=u-boot.bin\0" \
  114. "load=tftp ${loadaddr) ${u-boot}\0" \
  115. "upd=run load; run prog\0" \
  116. "prog=prot off ffe00000 ffe3ffff;" \
  117. "era ffe00000 ffe3ffff;" \
  118. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  119. "save\0" \
  120. ""
  121. #define CONFIG_PRAM 512 /* 512 KB */
  122. #define CFG_PROMPT "-> "
  123. #define CFG_LONGHELP /* undef to save memory */
  124. #if defined(CONFIG_KGDB)
  125. # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  126. #else
  127. # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  128. #endif
  129. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  130. #define CFG_MAXARGS 16 /* max number of command args */
  131. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  132. #define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000)
  133. #define CFG_HZ 1000
  134. #define CFG_CLK 75000000
  135. #define CFG_CPU_CLK CFG_CLK * 2
  136. #define CFG_MBAR 0x40000000
  137. /*
  138. * Low Level Configuration Settings
  139. * (address mappings, register initial values, etc.)
  140. * You should know what you are doing if you make changes here.
  141. */
  142. /*-----------------------------------------------------------------------
  143. * Definitions for initial stack pointer and data area (in DPRAM)
  144. */
  145. #define CFG_INIT_RAM_ADDR 0x20000000
  146. #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
  147. #define CFG_INIT_RAM_CTRL 0x21
  148. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  149. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
  150. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  151. /*-----------------------------------------------------------------------
  152. * Start addresses for the final memory configuration
  153. * (Set up by the startup code)
  154. * Please note that CFG_SDRAM_BASE _must_ start at 0
  155. */
  156. #define CFG_SDRAM_BASE 0x00000000
  157. #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
  158. #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
  159. #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
  160. #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
  161. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  162. #define CFG_BOOTPARAMS_LEN 64*1024
  163. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  164. /*
  165. * For booting Linux, the board info and command line data
  166. * have to be in the first 8 MB of memory, since this is
  167. * the maximum mapped by the Linux kernel during initialization ??
  168. */
  169. /* Initial Memory map for Linux */
  170. #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
  171. /*-----------------------------------------------------------------------
  172. * FLASH organization
  173. */
  174. #define CFG_FLASH_CFI
  175. #ifdef CFG_FLASH_CFI
  176. # define CFG_FLASH_CFI_DRIVER 1
  177. # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
  178. #ifdef NORFLASH_PS32BIT
  179. # define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  180. #else
  181. # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  182. #endif
  183. # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  184. # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  185. # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  186. #endif
  187. #define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
  188. /* Configuration for environment
  189. * Environment is embedded in u-boot in the second sector of the flash
  190. */
  191. #define CFG_ENV_IS_IN_FLASH 1
  192. #define CFG_ENV_IS_EMBEDDED 1
  193. #ifdef NORFLASH_PS32BIT
  194. # define CFG_ENV_OFFSET (0x8000)
  195. # define CFG_ENV_SIZE 0x4000
  196. # define CFG_ENV_SECT_SIZE 0x4000
  197. #else
  198. # define CFG_ENV_OFFSET (0x4000)
  199. # define CFG_ENV_SIZE 0x2000
  200. # define CFG_ENV_SECT_SIZE 0x2000
  201. #endif
  202. /*-----------------------------------------------------------------------
  203. * Cache Configuration
  204. */
  205. #define CFG_CACHELINE_SIZE 16
  206. /*-----------------------------------------------------------------------
  207. * Chipselect bank definitions
  208. */
  209. /*
  210. * CS0 - NOR Flash 1, 2, 4, or 8MB
  211. * CS1 - Available
  212. * CS2 - Available
  213. * CS3 - Available
  214. * CS4 - Available
  215. * CS5 - Available
  216. * CS6 - Available
  217. * CS7 - Available
  218. */
  219. #ifdef NORFLASH_PS32BIT
  220. # define CFG_CS0_BASE 0xFFC0
  221. # define CFG_CS0_MASK 0x003f0001
  222. # define CFG_CS0_CTRL 0x1D00
  223. #else
  224. # define CFG_CS0_BASE 0xFFE0
  225. # define CFG_CS0_MASK 0x001f0001
  226. # define CFG_CS0_CTRL 0x1D80
  227. #endif
  228. #endif /* _M5329EVB_H */