cm5200.h 4.4 KB

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  1. /*
  2. * (C) Copyright 2007 DENX Software Engineering
  3. *
  4. * Author: Bartlomiej Sieka <tur@semihalf.com>
  5. * Author: Grzegorz Bernacki <gjb@semihalf.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef _CM5200_H
  23. #define _CM5200_H
  24. /*
  25. * Definitions and declarations for the modules of the cm5200 platform. Mostly
  26. * related to reading the hardware identification data (HW ID) from the I2C
  27. * EEPROM, detection of the particular module we are executing on, and
  28. * appropriate SDRAM controller initialization.
  29. */
  30. #define CM5200_UNKNOWN_MODULE 0xffffffff
  31. enum {
  32. DEVICE_NAME, /* 0 */
  33. GENERATION, /* 1 */
  34. PCB_NAME, /* 2 */
  35. FORM, /* 3 */
  36. VERSION, /* 4 */
  37. IDENTIFICATION_NUMBER, /* 5 */
  38. MAJOR_SW_VERSION, /* 6 */
  39. MINOR_SW_VERSION, /* 7 */
  40. /* add new alements above this line */
  41. HW_ID_ELEM_COUNT /* count */
  42. };
  43. /*
  44. * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
  45. */
  46. #define DEVICE_NAME_OFFSET 0x02
  47. #define GENERATION_OFFSET 0x0b
  48. #define PCB_NAME_OFFSET 0x0c
  49. #define FORM_OFFSET 0x15
  50. #define VERSION_OFFSET 0x16
  51. #define IDENTIFICATION_NUMBER_OFFSET 0x19
  52. #define MAJOR_SW_VERSION_OFFSET 0x0480
  53. #define MINOR_SW_VERSION_OFFSET 0x0481
  54. #define DEVICE_NAME_LEN 0x09
  55. #define GENERATION_LEN 0x01
  56. #define PCB_NAME_LEN 0x09
  57. #define FORM_LEN 0x01
  58. #define VERSION_LEN 0x03
  59. #define IDENTIFICATION_NUMBER_LEN 0x09
  60. #define MAJOR_SW_VERSION_LEN 0x01
  61. #define MINOR_SW_VERSION_LEN 0x01
  62. #define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */
  63. /* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
  64. #define MODULE_NAME_MAXLEN 64
  65. /* storage for HW ID read from EEPROM */
  66. typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
  67. /* HW ID layout in EEPROM */
  68. static struct {
  69. unsigned int offset;
  70. unsigned int length;
  71. } hw_id_format[HW_ID_ELEM_COUNT] = {
  72. {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN},
  73. {GENERATION_OFFSET, GENERATION_LEN},
  74. {PCB_NAME_OFFSET, PCB_NAME_LEN},
  75. {FORM_OFFSET, FORM_LEN},
  76. {VERSION_OFFSET, VERSION_LEN},
  77. {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN},
  78. {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN},
  79. {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN},
  80. };
  81. /* HW ID data found in EEPROM on supported modules */
  82. static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
  83. "CM", /* DEVICE_NAME */
  84. "1", /* GENERATION */
  85. "CM1", /* PCB_NAME */
  86. "Q", /* FORM */
  87. "A", /* VERSION */
  88. "591881", /* IDENTIFICATION_NUMBER */
  89. "", /* MAJOR_SW_VERSION */
  90. "", /* MINOR_SW_VERSION */
  91. };
  92. static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
  93. "CM", /* DEVICE_NAME */
  94. "1", /* GENERATION */
  95. "CM11", /* PCB_NAME */
  96. "Q", /* FORM */
  97. "A", /* VERSION */
  98. "594200", /* IDENTIFICATION_NUMBER */
  99. "", /* MAJOR_SW_VERSION */
  100. "", /* MINOR_SW_VERSION */
  101. };
  102. static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
  103. "CMU", /* DEVICE_NAME */
  104. "1", /* GENERATION */
  105. "CMU1", /* PCB_NAME */
  106. "Q", /* FORM */
  107. "A", /* VERSION */
  108. "594128", /* IDENTIFICATION_NUMBER */
  109. "", /* MAJOR_SW_VERSION */
  110. "", /* MINOR_SW_VERSION */
  111. };
  112. /* list of known modules */
  113. static char **hw_id_list[] = {
  114. cm1_qa_hw_id,
  115. cm11_qa_hw_id,
  116. cmu1_qa_hw_id,
  117. };
  118. /* indices to the above list - keep in sync */
  119. enum {
  120. CM1_QA,
  121. CM11_QA,
  122. CMU1_QA,
  123. };
  124. /* identify modules based on these hw id elements */
  125. static int hw_id_identify[] = {
  126. PCB_NAME,
  127. FORM,
  128. VERSION,
  129. };
  130. /* Registers' settings for SDRAM controller intialization */
  131. typedef struct {
  132. ulong mode;
  133. ulong control;
  134. ulong config1;
  135. ulong config2;
  136. } mem_conf_t;
  137. static mem_conf_t k4s561632E = {
  138. 0x00CD0000, /* CASL 3, burst length 8 */
  139. 0x514F0000,
  140. 0xE2333900,
  141. 0x8EE70000
  142. };
  143. static mem_conf_t mt48lc32m16a2 = {
  144. 0x00CD0000, /* CASL 3, burst length 8 */
  145. 0x514F0000,
  146. 0xD2322800,
  147. 0x8AD70000
  148. };
  149. static mem_conf_t* memory_config[] = {
  150. &k4s561632E,
  151. &mt48lc32m16a2
  152. };
  153. #endif /* _CM5200_H */