xparameters.h 2.1 KB

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  1. /*
  2. * (C) Copyright 2007 Michal Simek
  3. *
  4. * Michal SIMEK <monstr@monstr.eu>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. *
  24. * CAUTION: This file is automatically generated by libgen.
  25. * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
  26. */
  27. /* System Clock Frequency */
  28. #define XILINX_CLOCK_FREQ 100000000
  29. /* Interrupt controller is opb_intc_0 */
  30. #define XILINX_INTC_BASEADDR 0x41200000
  31. #define XILINX_INTC_NUM_INTR_INPUTS 11
  32. /* Timer pheriphery is opb_timer_1 */
  33. #define XILINX_TIMER_BASEADDR 0x41c00000
  34. #define XILINX_TIMER_IRQ 1
  35. /* Uart pheriphery is RS232_Uart_1 */
  36. #define XILINX_UART_BASEADDR 0x40600000
  37. #define XILINX_UART_BAUDRATE 115200
  38. /* GPIO is LEDs_4Bit*/
  39. #define XILINX_GPIO_BASEADDR 0x40000000
  40. /* FLASH doesn't exist none */
  41. /* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
  42. #define XILINX_RAM_START 0x30000000
  43. #define XILINX_RAM_SIZE 0x10000000
  44. /* Sysace Controller is SysACE_CompactFlash */
  45. #define XILINX_SYSACE_BASEADDR 0x41800000
  46. #define XILINX_SYSACE_HIGHADDR 0x4180ffff
  47. #define XILINX_SYSACE_MEM_WIDTH 16
  48. /* Ethernet controller is Ethernet_MAC */
  49. #define XPAR_XEMAC_NUM_INSTANCES 1
  50. #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
  51. #define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
  52. #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
  53. #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
  54. #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
  55. #define XPAR_OPB_ETHERNET_0_MII_EXIST 1