canyonlands.c 11 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. #include <common.h>
  21. #include <ppc440.h>
  22. #include <libfdt.h>
  23. #include <fdt_support.h>
  24. #include <asm/processor.h>
  25. #include <asm/io.h>
  26. #include <asm/mmu.h>
  27. #include <asm/4xx_pcie.h>
  28. extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  29. DECLARE_GLOBAL_DATA_PTR;
  30. int board_early_init_f(void)
  31. {
  32. u32 sdr0_cust0;
  33. /*------------------------------------------------------------------+
  34. * Setup the interrupt controller polarities, triggers, etc.
  35. *------------------------------------------------------------------*/
  36. mtdcr(uic0sr, 0xffffffff); /* clear all */
  37. mtdcr(uic0er, 0x00000000); /* disable all */
  38. mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
  39. mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
  40. mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
  41. mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
  42. mtdcr(uic0sr, 0xffffffff); /* clear all */
  43. mtdcr(uic1sr, 0xffffffff); /* clear all */
  44. mtdcr(uic1er, 0x00000000); /* disable all */
  45. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  46. mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
  47. mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
  48. mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
  49. mtdcr(uic1sr, 0xffffffff); /* clear all */
  50. mtdcr(uic2sr, 0xffffffff); /* clear all */
  51. mtdcr(uic2er, 0x00000000); /* disable all */
  52. mtdcr(uic2cr, 0x00000000); /* all non-critical */
  53. mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
  54. mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
  55. mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
  56. mtdcr(uic2sr, 0xffffffff); /* clear all */
  57. mtdcr(uic3sr, 0xffffffff); /* clear all */
  58. mtdcr(uic3er, 0x00000000); /* disable all */
  59. mtdcr(uic3cr, 0x00000000); /* all non-critical */
  60. mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
  61. mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
  62. mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
  63. mtdcr(uic3sr, 0xffffffff); /* clear all */
  64. /* SDR Setting - enable NDFC */
  65. mfsdr(SDR0_CUST0, sdr0_cust0);
  66. sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
  67. SDR0_CUST0_NDFC_ENABLE |
  68. SDR0_CUST0_NDFC_BW_8_BIT |
  69. SDR0_CUST0_NDFC_ARE_MASK |
  70. SDR0_CUST0_NDFC_BAC_ENCODE(3) |
  71. (0x80000000 >> (28 + CFG_NAND_CS));
  72. mtsdr(SDR0_CUST0, sdr0_cust0);
  73. /*
  74. * Configure PFC (Pin Function Control) registers
  75. * UART0: 4 pins
  76. */
  77. mtsdr(SDR0_PFC1, 0x00040000);
  78. /* Enable PCI host functionality in SDR0_PCI0 */
  79. mtsdr(SDR0_PCI0, 0xe0000000);
  80. /* Enable ethernet and take out of reset */
  81. out_8((void *)CFG_BCSR_BASE + 6, 0);
  82. /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
  83. out_8((void *)CFG_BCSR_BASE + 5, 0);
  84. /* Enable USB host & USB-OTG */
  85. out_8((void *)CFG_BCSR_BASE + 7, 0);
  86. mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
  87. return 0;
  88. }
  89. int checkboard (void)
  90. {
  91. char *s = getenv("serial#");
  92. u32 pvr = get_pvr();
  93. if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
  94. printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
  95. else
  96. printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
  97. if (s != NULL) {
  98. puts(", serial# ");
  99. puts(s);
  100. }
  101. putc('\n');
  102. return (0);
  103. }
  104. /*
  105. * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  106. * board specific values.
  107. */
  108. u32 ddr_wrdtr(u32 default_val) {
  109. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  110. }
  111. u32 ddr_clktr(u32 default_val) {
  112. return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  113. }
  114. #if defined(CONFIG_NAND_U_BOOT)
  115. /*
  116. * NAND booting U-Boot version uses a fixed initialization, since the whole
  117. * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
  118. * code.
  119. */
  120. long int initdram(int board_type)
  121. {
  122. return CFG_MBYTES_SDRAM << 20;
  123. }
  124. #endif
  125. #if defined(CFG_DRAM_TEST)
  126. int testdram(void)
  127. {
  128. unsigned long *mem = (unsigned long *)0;
  129. const unsigned long kend = (1024 / sizeof(unsigned long));
  130. unsigned long k, n;
  131. mtmsr(0);
  132. for (k = 0; k < CFG_KBYTES_SDRAM;
  133. ++k, mem += (1024 / sizeof(unsigned long))) {
  134. if ((k & 1023) == 0) {
  135. printf("%3d MB\r", k / 1024);
  136. }
  137. memset(mem, 0xaaaaaaaa, 1024);
  138. for (n = 0; n < kend; ++n) {
  139. if (mem[n] != 0xaaaaaaaa) {
  140. printf("SDRAM test fails at: %08x\n",
  141. (uint) & mem[n]);
  142. return 1;
  143. }
  144. }
  145. memset(mem, 0x55555555, 1024);
  146. for (n = 0; n < kend; ++n) {
  147. if (mem[n] != 0x55555555) {
  148. printf("SDRAM test fails at: %08x\n",
  149. (uint) & mem[n]);
  150. return 1;
  151. }
  152. }
  153. }
  154. printf("SDRAM test passes\n");
  155. return 0;
  156. }
  157. #endif
  158. /*************************************************************************
  159. * pci_target_init
  160. *
  161. * The bootstrap configuration provides default settings for the pci
  162. * inbound map (PIM). But the bootstrap config choices are limited and
  163. * may not be sufficient for a given board.
  164. *
  165. ************************************************************************/
  166. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  167. void pci_target_init(struct pci_controller * hose )
  168. {
  169. /*-------------------------------------------------------------------+
  170. * Disable everything
  171. *-------------------------------------------------------------------*/
  172. out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
  173. out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
  174. out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
  175. out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
  176. /*-------------------------------------------------------------------+
  177. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  178. * strapping options to not support sizes such as 128/256 MB.
  179. *-------------------------------------------------------------------*/
  180. out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
  181. out_le32((void *)PCIX0_PIM0LAH, 0);
  182. out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
  183. out_le32((void *)PCIX0_BAR0, 0);
  184. /*-------------------------------------------------------------------+
  185. * Program the board's subsystem id/vendor id
  186. *-------------------------------------------------------------------*/
  187. out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
  188. out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
  189. out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
  190. }
  191. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  192. #if defined(CONFIG_PCI)
  193. /*
  194. * is_pci_host
  195. *
  196. * This routine is called to determine if a pci scan should be
  197. * performed. With various hardware environments (especially cPCI and
  198. * PPMC) it's insufficient to depend on the state of the arbiter enable
  199. * bit in the strap register, or generic host/adapter assumptions.
  200. *
  201. * Rather than hard-code a bad assumption in the general 440 code, the
  202. * 440 pci code requires the board to decide at runtime.
  203. *
  204. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  205. */
  206. int is_pci_host(struct pci_controller *hose)
  207. {
  208. /* Board is always configured as host. */
  209. return (1);
  210. }
  211. static struct pci_controller pcie_hose[2] = {{0},{0}};
  212. void pcie_setup_hoses(int busno)
  213. {
  214. struct pci_controller *hose;
  215. int i, bus;
  216. int ret = 0;
  217. char *env;
  218. unsigned int delay;
  219. /*
  220. * assume we're called after the PCIX hose is initialized, which takes
  221. * bus ID 0 and therefore start numbering PCIe's from 1.
  222. */
  223. bus = busno;
  224. for (i = 0; i <= 1; i++) {
  225. if (is_end_point(i))
  226. ret = ppc4xx_init_pcie_endport(i);
  227. else
  228. ret = ppc4xx_init_pcie_rootport(i);
  229. if (ret) {
  230. printf("PCIE%d: initialization as %s failed\n", i,
  231. is_end_point(i) ? "endpoint" : "root-complex");
  232. continue;
  233. }
  234. hose = &pcie_hose[i];
  235. hose->first_busno = bus;
  236. hose->last_busno = bus;
  237. hose->current_busno = bus;
  238. /* setup mem resource */
  239. pci_set_region(hose->regions + 0,
  240. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  241. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  242. CFG_PCIE_MEMSIZE,
  243. PCI_REGION_MEM);
  244. hose->region_count = 1;
  245. pci_register_hose(hose);
  246. if (is_end_point(i)) {
  247. ppc4xx_setup_pcie_endpoint(hose, i);
  248. /*
  249. * Reson for no scanning is endpoint can not generate
  250. * upstream configuration accesses.
  251. */
  252. } else {
  253. ppc4xx_setup_pcie_rootpoint(hose, i);
  254. env = getenv ("pciscandelay");
  255. if (env != NULL) {
  256. delay = simple_strtoul(env, NULL, 10);
  257. if (delay > 5)
  258. printf("Warning, expect noticable delay before "
  259. "PCIe scan due to 'pciscandelay' value!\n");
  260. mdelay(delay * 1000);
  261. }
  262. /*
  263. * Config access can only go down stream
  264. */
  265. hose->last_busno = pci_hose_scan(hose);
  266. bus = hose->last_busno + 1;
  267. }
  268. }
  269. }
  270. #endif /* CONFIG_PCI */
  271. int board_early_init_r (void)
  272. {
  273. /*
  274. * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
  275. * boot EBC mapping only supports a maximum of 16MBytes
  276. * (4.ff00.0000 - 4.ffff.ffff).
  277. * To solve this problem, the FLASH has to get remapped to another
  278. * EBC address which accepts bigger regions:
  279. *
  280. * 0xfc00.0000 -> 4.cc00.0000
  281. */
  282. /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
  283. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  284. mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
  285. #else
  286. mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
  287. #endif
  288. /* Remove TLB entry of boot EBC mapping */
  289. remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
  290. /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
  291. program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
  292. TLB_WORD2_I_ENABLE);
  293. /*
  294. * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
  295. * 0xfc00.0000 is possible
  296. */
  297. /*
  298. * Clear potential errors resulting from auto-calibration.
  299. * If not done, then we could get an interrupt later on when
  300. * exceptions are enabled.
  301. */
  302. set_mcsr(get_mcsr());
  303. return 0;
  304. }
  305. int misc_init_r(void)
  306. {
  307. u32 sdr0_srst1 = 0;
  308. u32 eth_cfg;
  309. /*
  310. * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
  311. * This is board specific, so let's do it here.
  312. */
  313. mfsdr(SDR0_ETH_CFG, eth_cfg);
  314. /* disable SGMII mode */
  315. eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
  316. SDR0_ETH_CFG_SGMII1_ENABLE |
  317. SDR0_ETH_CFG_SGMII0_ENABLE);
  318. /* Set the for 2 RGMII mode */
  319. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  320. eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
  321. eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  322. mtsdr(SDR0_ETH_CFG, eth_cfg);
  323. /*
  324. * The AHB Bridge core is held in reset after power-on or reset
  325. * so enable it now
  326. */
  327. mfsdr(SDR0_SRST1, sdr0_srst1);
  328. sdr0_srst1 &= ~SDR0_SRST1_AHB;
  329. mtsdr(SDR0_SRST1, sdr0_srst1);
  330. return 0;
  331. }
  332. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  333. void ft_board_setup(void *blob, bd_t *bd)
  334. {
  335. u32 val[4];
  336. int rc;
  337. ft_cpu_setup(blob, bd);
  338. /* Fixup NOR mapping */
  339. val[0] = 0; /* chip select number */
  340. val[1] = 0; /* always 0 */
  341. val[2] = gd->bd->bi_flashstart;
  342. val[3] = gd->bd->bi_flashsize;
  343. rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
  344. val, sizeof(val), 1);
  345. if (rc)
  346. printf("Unable to update property NOR mapping, err=%s\n",
  347. fdt_strerror(rc));
  348. }
  349. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */