canyonlands.c 14 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. #include <common.h>
  21. #include <asm/ppc440.h>
  22. #include <libfdt.h>
  23. #include <fdt_support.h>
  24. #include <i2c.h>
  25. #include <asm/processor.h>
  26. #include <asm/io.h>
  27. #include <asm/mmu.h>
  28. #include <asm/4xx_pcie.h>
  29. #include <asm/ppc4xx-gpio.h>
  30. #include <asm/errno.h>
  31. extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  32. DECLARE_GLOBAL_DATA_PTR;
  33. struct board_bcsr {
  34. u8 board_id;
  35. u8 cpld_rev;
  36. u8 led_user;
  37. u8 board_status;
  38. u8 reset_ctrl;
  39. u8 flash_ctrl;
  40. u8 eth_ctrl;
  41. u8 usb_ctrl;
  42. u8 irq_ctrl;
  43. };
  44. #define BOARD_CANYONLANDS_PCIE 1
  45. #define BOARD_CANYONLANDS_SATA 2
  46. #define BOARD_GLACIER 3
  47. #define BOARD_ARCHES 4
  48. /*
  49. * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
  50. * board specific values.
  51. */
  52. #if defined(CONFIG_ARCHES)
  53. u32 ddr_wrdtr(u32 default_val) {
  54. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
  55. }
  56. #else
  57. u32 ddr_wrdtr(u32 default_val) {
  58. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  59. }
  60. u32 ddr_clktr(u32 default_val) {
  61. return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  62. }
  63. #endif
  64. #if defined(CONFIG_ARCHES)
  65. /*
  66. * FPGA read/write helper macros
  67. */
  68. static inline int board_fpga_read(int offset)
  69. {
  70. int data;
  71. data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
  72. return data;
  73. }
  74. static inline void board_fpga_write(int offset, int data)
  75. {
  76. out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
  77. }
  78. /*
  79. * CPLD read/write helper macros
  80. */
  81. static inline int board_cpld_read(int offset)
  82. {
  83. int data;
  84. out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  85. data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
  86. return data;
  87. }
  88. static inline void board_cpld_write(int offset, int data)
  89. {
  90. out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  91. out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
  92. }
  93. #else
  94. static int pvr_460ex(void)
  95. {
  96. u32 pvr = get_pvr();
  97. if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
  98. (pvr == PVR_460EX_RB))
  99. return 1;
  100. return 0;
  101. }
  102. #endif /* defined(CONFIG_ARCHES) */
  103. int board_early_init_f(void)
  104. {
  105. #if !defined(CONFIG_ARCHES)
  106. u32 sdr0_cust0;
  107. struct board_bcsr *bcsr_data =
  108. (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
  109. #endif
  110. /*
  111. * Setup the interrupt controller polarities, triggers, etc.
  112. */
  113. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  114. mtdcr(UIC0ER, 0x00000000); /* disable all */
  115. mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
  116. mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
  117. mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
  118. mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
  119. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  120. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  121. mtdcr(UIC1ER, 0x00000000); /* disable all */
  122. mtdcr(UIC1CR, 0x00000000); /* all non-critical */
  123. mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
  124. mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
  125. mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
  126. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  127. mtdcr(UIC2SR, 0xffffffff); /* clear all */
  128. mtdcr(UIC2ER, 0x00000000); /* disable all */
  129. mtdcr(UIC2CR, 0x00000000); /* all non-critical */
  130. mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
  131. mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
  132. mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
  133. mtdcr(UIC2SR, 0xffffffff); /* clear all */
  134. mtdcr(UIC3SR, 0xffffffff); /* clear all */
  135. mtdcr(UIC3ER, 0x00000000); /* disable all */
  136. mtdcr(UIC3CR, 0x00000000); /* all non-critical */
  137. mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
  138. mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
  139. mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
  140. mtdcr(UIC3SR, 0xffffffff); /* clear all */
  141. #if !defined(CONFIG_ARCHES)
  142. /* SDR Setting - enable NDFC */
  143. mfsdr(SDR0_CUST0, sdr0_cust0);
  144. sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
  145. SDR0_CUST0_NDFC_ENABLE |
  146. SDR0_CUST0_NDFC_BW_8_BIT |
  147. SDR0_CUST0_NDFC_ARE_MASK |
  148. SDR0_CUST0_NDFC_BAC_ENCODE(3) |
  149. (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
  150. mtsdr(SDR0_CUST0, sdr0_cust0);
  151. #endif
  152. /*
  153. * Configure PFC (Pin Function Control) registers
  154. * UART0: 4 pins
  155. */
  156. mtsdr(SDR0_PFC1, 0x00040000);
  157. /* Enable PCI host functionality in SDR0_PCI0 */
  158. mtsdr(SDR0_PCI0, 0xe0000000);
  159. #if !defined(CONFIG_ARCHES)
  160. /* Enable ethernet and take out of reset */
  161. out_8(&bcsr_data->eth_ctrl, 0) ;
  162. /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
  163. out_8(&bcsr_data->flash_ctrl, 0) ;
  164. mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
  165. /* Setup PLB4-AHB bridge based on the system address map */
  166. mtdcr(AHB_TOP, 0x8000004B);
  167. mtdcr(AHB_BOT, 0x8000004B);
  168. #endif
  169. return 0;
  170. }
  171. #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
  172. int usb_board_init(void)
  173. {
  174. struct board_bcsr *bcsr_data =
  175. (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
  176. u8 val;
  177. /* Enable USB host & USB-OTG */
  178. val = in_8(&bcsr_data->usb_ctrl);
  179. val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
  180. out_8(&bcsr_data->usb_ctrl, val);
  181. /*
  182. * Configure USB-STP pins as alternate and not GPIO
  183. * It seems to be neccessary to configure the STP pins as GPIO
  184. * input at powerup (perhaps while USB reset is asserted). So
  185. * we configure those pins to their "real" function now.
  186. */
  187. gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  188. gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  189. return 0;
  190. }
  191. int usb_board_stop(void)
  192. {
  193. struct board_bcsr *bcsr_data =
  194. (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
  195. u8 val;
  196. /* Disable USB host & USB-OTG */
  197. val = in_8(&bcsr_data->usb_ctrl);
  198. val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
  199. out_8(&bcsr_data->usb_ctrl, val);
  200. /* Reconfigure USB-STP pins as input */
  201. gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
  202. gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
  203. return 0;
  204. }
  205. int usb_board_init_fail(void)
  206. {
  207. return usb_board_stop();
  208. }
  209. #endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
  210. #if !defined(CONFIG_ARCHES)
  211. static void canyonlands_sata_init(int board_type)
  212. {
  213. u32 reg;
  214. if (board_type == BOARD_CANYONLANDS_SATA) {
  215. /* Put SATA in reset */
  216. SDR_WRITE(SDR0_SRST1, 0x00020001);
  217. /* Set the phy for SATA, not PCI-E port 0 */
  218. reg = SDR_READ(PESDR0_PHY_CTL_RST);
  219. SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
  220. reg = SDR_READ(PESDR0_L0CLK);
  221. SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
  222. SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
  223. SDR_WRITE(PESDR0_L0DRV, 0x00000104);
  224. /* Bring SATA out of reset */
  225. SDR_WRITE(SDR0_SRST1, 0x00000000);
  226. }
  227. }
  228. #endif /* !defined(CONFIG_ARCHES) */
  229. int get_cpu_num(void)
  230. {
  231. int cpu = NA_OR_UNKNOWN_CPU;
  232. #if defined(CONFIG_ARCHES)
  233. int cpu_num;
  234. cpu_num = board_fpga_read(0x3);
  235. /* sanity check; assume cpu numbering starts and increments from 0 */
  236. if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
  237. cpu = cpu_num;
  238. #endif
  239. return cpu;
  240. }
  241. #if !defined(CONFIG_ARCHES)
  242. int checkboard(void)
  243. {
  244. struct board_bcsr *bcsr_data =
  245. (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
  246. char *s = getenv("serial#");
  247. if (pvr_460ex()) {
  248. printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
  249. if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
  250. gd->board_type = BOARD_CANYONLANDS_PCIE;
  251. else
  252. gd->board_type = BOARD_CANYONLANDS_SATA;
  253. } else {
  254. printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
  255. gd->board_type = BOARD_GLACIER;
  256. }
  257. switch (gd->board_type) {
  258. case BOARD_CANYONLANDS_PCIE:
  259. case BOARD_GLACIER:
  260. puts(", 2*PCIe");
  261. break;
  262. case BOARD_CANYONLANDS_SATA:
  263. puts(", 1*PCIe/1*SATA");
  264. break;
  265. }
  266. printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
  267. if (s != NULL) {
  268. puts(", serial# ");
  269. puts(s);
  270. }
  271. putc('\n');
  272. canyonlands_sata_init(gd->board_type);
  273. return (0);
  274. }
  275. #else /* defined(CONFIG_ARCHES) */
  276. int checkboard(void)
  277. {
  278. char *s = getenv("serial#");
  279. printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
  280. printf(" Revision %02x.%02x ",
  281. board_fpga_read(0x0), board_fpga_read(0x1));
  282. gd->board_type = BOARD_ARCHES;
  283. /* Only CPU0 has access to CPLD registers */
  284. if (get_cpu_num() == 0) {
  285. u8 cfg_sw = board_cpld_read(0x1);
  286. printf("(FPGA=%02x, CPLD=%02x)\n",
  287. board_fpga_read(0x2), board_cpld_read(0x0));
  288. printf(" Configuration Switch %d%d%d%d\n",
  289. ((cfg_sw >> 3) & 0x01),
  290. ((cfg_sw >> 2) & 0x01),
  291. ((cfg_sw >> 1) & 0x01),
  292. ((cfg_sw >> 0) & 0x01));
  293. } else
  294. printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
  295. if (s != NULL)
  296. printf(" Serial# %s\n", s);
  297. return 0;
  298. }
  299. #endif /* !defined(CONFIG_ARCHES) */
  300. #if defined(CONFIG_NAND_U_BOOT)
  301. /*
  302. * NAND booting U-Boot version uses a fixed initialization, since the whole
  303. * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
  304. * code.
  305. */
  306. phys_size_t initdram(int board_type)
  307. {
  308. return CONFIG_SYS_MBYTES_SDRAM << 20;
  309. }
  310. #endif
  311. #if defined(CONFIG_PCI)
  312. int board_pcie_first(void)
  313. {
  314. /*
  315. * Canyonlands with SATA enabled has only one PCIe slot
  316. * (2nd one).
  317. */
  318. if (gd->board_type == BOARD_CANYONLANDS_SATA)
  319. return 1;
  320. return 0;
  321. }
  322. #endif /* CONFIG_PCI */
  323. int board_early_init_r (void)
  324. {
  325. /*
  326. * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
  327. * boot EBC mapping only supports a maximum of 16MBytes
  328. * (4.ff00.0000 - 4.ffff.ffff).
  329. * To solve this problem, the FLASH has to get remapped to another
  330. * EBC address which accepts bigger regions:
  331. *
  332. * 0xfc00.0000 -> 4.cc00.0000
  333. */
  334. /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
  335. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  336. mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  337. #else
  338. mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  339. #endif
  340. /* Remove TLB entry of boot EBC mapping */
  341. remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
  342. /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
  343. program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
  344. TLB_WORD2_I_ENABLE);
  345. /*
  346. * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
  347. * 0xfc00.0000 is possible
  348. */
  349. /*
  350. * Clear potential errors resulting from auto-calibration.
  351. * If not done, then we could get an interrupt later on when
  352. * exceptions are enabled.
  353. */
  354. set_mcsr(get_mcsr());
  355. return 0;
  356. }
  357. #if !defined(CONFIG_ARCHES)
  358. int misc_init_r(void)
  359. {
  360. u32 sdr0_srst1 = 0;
  361. u32 eth_cfg;
  362. u8 val;
  363. /*
  364. * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
  365. * This is board specific, so let's do it here.
  366. */
  367. mfsdr(SDR0_ETH_CFG, eth_cfg);
  368. /* disable SGMII mode */
  369. eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
  370. SDR0_ETH_CFG_SGMII1_ENABLE |
  371. SDR0_ETH_CFG_SGMII0_ENABLE);
  372. /* Set the for 2 RGMII mode */
  373. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  374. eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
  375. if (pvr_460ex())
  376. eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  377. else
  378. eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  379. mtsdr(SDR0_ETH_CFG, eth_cfg);
  380. /*
  381. * The AHB Bridge core is held in reset after power-on or reset
  382. * so enable it now
  383. */
  384. mfsdr(SDR0_SRST1, sdr0_srst1);
  385. sdr0_srst1 &= ~SDR0_SRST1_AHB;
  386. mtsdr(SDR0_SRST1, sdr0_srst1);
  387. /*
  388. * RTC/M41T62:
  389. * Disable square wave output: Batterie will be drained
  390. * quickly, when this output is not disabled
  391. */
  392. val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
  393. val &= ~0x40;
  394. i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
  395. return 0;
  396. }
  397. #else /* defined(CONFIG_ARCHES) */
  398. int misc_init_r(void)
  399. {
  400. u32 eth_cfg = 0;
  401. u32 eth_pll;
  402. u32 reg;
  403. /*
  404. * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
  405. * This is board specific, so let's do it here.
  406. */
  407. /* enable SGMII mode */
  408. eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
  409. SDR0_ETH_CFG_SGMII1_ENABLE |
  410. SDR0_ETH_CFG_SGMII2_ENABLE);
  411. /* Set EMAC for MDIO */
  412. eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
  413. /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
  414. eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  415. mtsdr(SDR0_ETH_CFG, eth_cfg);
  416. /* reset all SGMII interfaces */
  417. mfsdr(SDR0_SRST1, reg);
  418. reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
  419. mtsdr(SDR0_SRST1, reg);
  420. mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
  421. mtsdr(SDR0_SRST1, 0x00000000);
  422. do {
  423. mfsdr(SDR0_ETH_PLL, eth_pll);
  424. } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
  425. return 0;
  426. }
  427. #endif /* !defined(CONFIG_ARCHES) */
  428. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  429. extern void __ft_board_setup(void *blob, bd_t *bd);
  430. void ft_board_setup(void *blob, bd_t *bd)
  431. {
  432. __ft_board_setup(blob, bd);
  433. if (gd->board_type == BOARD_CANYONLANDS_SATA) {
  434. /*
  435. * When SATA is selected we need to disable the first PCIe
  436. * node in the device tree, so that Linux doesn't initialize
  437. * it.
  438. */
  439. fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
  440. "disabled", sizeof("disabled"), 1);
  441. }
  442. if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
  443. /*
  444. * When PCIe is selected we need to disable the SATA
  445. * node in the device tree, so that Linux doesn't initialize
  446. * it.
  447. */
  448. fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
  449. "disabled", sizeof("disabled"), 1);
  450. }
  451. }
  452. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */