start.S 8.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426
  1. /*
  2. * armboot - Startup Code for ARM926EJS CPU-core
  3. *
  4. * Copyright (c) 2003 Texas Instruments
  5. *
  6. * ----- Adapted for OMAP1610 from ARM925t code ------
  7. *
  8. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  9. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  10. * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
  11. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  12. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. */
  32. #include <config.h>
  33. #include <version.h>
  34. #if defined(CONFIG_OMAP1610)
  35. #include <./configs/omap1510.h>
  36. #endif
  37. /*
  38. *************************************************************************
  39. *
  40. * Jump vector table as in table 3.1 in [1]
  41. *
  42. *************************************************************************
  43. */
  44. .globl _start
  45. _start:
  46. b reset
  47. ldr pc, _undefined_instruction
  48. ldr pc, _software_interrupt
  49. ldr pc, _prefetch_abort
  50. ldr pc, _data_abort
  51. ldr pc, _not_used
  52. ldr pc, _irq
  53. ldr pc, _fiq
  54. _undefined_instruction:
  55. .word undefined_instruction
  56. _software_interrupt:
  57. .word software_interrupt
  58. _prefetch_abort:
  59. .word prefetch_abort
  60. _data_abort:
  61. .word data_abort
  62. _not_used:
  63. .word not_used
  64. _irq:
  65. .word irq
  66. _fiq:
  67. .word fiq
  68. .balignl 16,0xdeadbeef
  69. /*
  70. *************************************************************************
  71. *
  72. * Startup Code (reset vector)
  73. *
  74. * do important init only if we don't start from memory!
  75. * setup Memory and board specific bits prior to relocation.
  76. * relocate armboot to ram
  77. * setup stack
  78. *
  79. *************************************************************************
  80. */
  81. /*
  82. * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  83. */
  84. _TEXT_BASE:
  85. .word TEXT_BASE
  86. .globl _armboot_start
  87. _armboot_start:
  88. .word _start
  89. /*
  90. * Note: _armboot_end_data and _armboot_end are defined
  91. * by the (board-dependent) linker script.
  92. * _armboot_end_data is the first usable FLASH address after armboot
  93. */
  94. .globl _armboot_end_data
  95. _armboot_end_data:
  96. .word armboot_end_data
  97. .globl _armboot_end
  98. _armboot_end:
  99. .word armboot_end
  100. /*
  101. * _armboot_real_end is the first usable RAM address behind armboot
  102. * and the various stacks
  103. */
  104. .globl _armboot_real_end
  105. _armboot_real_end:
  106. .word 0x0badc0de
  107. #ifdef CONFIG_USE_IRQ
  108. /* IRQ stack memory (calculated at run-time) */
  109. .globl IRQ_STACK_START
  110. IRQ_STACK_START:
  111. .word 0x0badc0de
  112. /* IRQ stack memory (calculated at run-time) */
  113. .globl FIQ_STACK_START
  114. FIQ_STACK_START:
  115. .word 0x0badc0de
  116. #endif
  117. /*
  118. * the actual reset code
  119. */
  120. reset:
  121. /*
  122. * set the cpu to SVC32 mode
  123. */
  124. mrs r0,cpsr
  125. bic r0,r0,#0x1f
  126. orr r0,r0,#0xd3
  127. msr cpsr,r0
  128. /*
  129. * turn off the watchdog, unlock/diable sequence
  130. */
  131. mov r1, #0xF5
  132. ldr r0, =WDTIM_MODE
  133. strh r1, [r0]
  134. mov r1, #0xA0
  135. strh r1, [r0]
  136. /*
  137. * mask all IRQs by setting all bits in the INTMR - default
  138. */
  139. mov r1, #0xffffffff
  140. ldr r0, =REG_IHL1_MIR
  141. str r1, [r0]
  142. ldr r0, =REG_IHL2_MIR
  143. str r1, [r0]
  144. bl cpu_init_crit
  145. relocate:
  146. /*
  147. * relocate armboot to RAM
  148. */
  149. adr r0, _start /* r0 <- current position of code */
  150. ldr r2, _armboot_start
  151. ldr r3, _armboot_end
  152. sub r2, r3, r2 /* r2 <- size of armboot */
  153. ldr r1, _TEXT_BASE /* r1 <- destination address */
  154. add r2, r0, r2 /* r2 <- source end address */
  155. /*
  156. * r0 = source address
  157. * r1 = target address
  158. * r2 = source end address
  159. */
  160. copy_loop:
  161. ldmia r0!, {r3-r10}
  162. stmia r1!, {r3-r10}
  163. cmp r0, r2
  164. ble copy_loop
  165. /* set up the stack */
  166. ldr r0, _armboot_end
  167. add r0, r0, #CONFIG_STACKSIZE
  168. sub sp, r0, #12 /* leave 3 words for abort-stack */
  169. ldr pc, _start_armboot
  170. _start_armboot:
  171. .word start_armboot
  172. /*
  173. *************************************************************************
  174. *
  175. * CPU_init_critical registers
  176. *
  177. * setup important registers
  178. * setup memory timing
  179. *
  180. *************************************************************************
  181. */
  182. cpu_init_crit:
  183. /*
  184. * flush v4 I/D caches
  185. */
  186. mov r0, #0
  187. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  188. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  189. /*
  190. * disable MMU stuff and caches
  191. */
  192. mrc p15, 0, r0, c1, c0, 0
  193. bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
  194. bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
  195. orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
  196. orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
  197. mcr p15, 0, r0, c1, c0, 0
  198. /*
  199. * Go setup Memory and board specific bits prior to relocation.
  200. */
  201. mov ip, lr /* perserve link reg across call */
  202. bl platformsetup /* go setup pll,mux,memory */
  203. mov lr, ip /* restore link */
  204. mov pc, lr /* back to my caller */
  205. /*
  206. *************************************************************************
  207. *
  208. * Interrupt handling
  209. *
  210. *************************************************************************
  211. */
  212. @
  213. @ IRQ stack frame.
  214. @
  215. #define S_FRAME_SIZE 72
  216. #define S_OLD_R0 68
  217. #define S_PSR 64
  218. #define S_PC 60
  219. #define S_LR 56
  220. #define S_SP 52
  221. #define S_IP 48
  222. #define S_FP 44
  223. #define S_R10 40
  224. #define S_R9 36
  225. #define S_R8 32
  226. #define S_R7 28
  227. #define S_R6 24
  228. #define S_R5 20
  229. #define S_R4 16
  230. #define S_R3 12
  231. #define S_R2 8
  232. #define S_R1 4
  233. #define S_R0 0
  234. #define MODE_SVC 0x13
  235. #define I_BIT 0x80
  236. /*
  237. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  238. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  239. */
  240. .macro bad_save_user_regs
  241. @ carve out a frame on current user stack
  242. sub sp, sp, #S_FRAME_SIZE
  243. stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  244. ldr r2, _armboot_end @ find top of stack
  245. add r2, r2, #CONFIG_STACKSIZE @ find base of normal stack
  246. sub r2, r2, #8 @ set base 2 words into abort stack
  247. @ get values for "aborted" pc and cpsr (into parm regs)
  248. ldmia r2, {r2 - r3}
  249. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  250. add r5, sp, #S_SP
  251. mov r1, lr
  252. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  253. mov r0, sp @ save current stack into r0 (param register)
  254. .endm
  255. .macro irq_save_user_regs
  256. sub sp, sp, #S_FRAME_SIZE
  257. stmia sp, {r0 - r12} @ Calling r0-r12
  258. @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  259. add r8, sp, #S_PC
  260. stmdb r8, {sp, lr}^ @ Calling SP, LR
  261. str lr, [r8, #0] @ Save calling PC
  262. mrs r6, spsr
  263. str r6, [r8, #4] @ Save CPSR
  264. str r0, [r8, #8] @ Save OLD_R0
  265. mov r0, sp
  266. .endm
  267. .macro irq_restore_user_regs
  268. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  269. mov r0, r0
  270. ldr lr, [sp, #S_PC] @ Get PC
  271. add sp, sp, #S_FRAME_SIZE
  272. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  273. .endm
  274. .macro get_bad_stack
  275. @ get bottom of stack (into sp by by user stack pointer).
  276. ldr r13, _armboot_end
  277. @ head to reserved words at the top of the stack
  278. add r13, r13, #CONFIG_STACKSIZE
  279. sub r13, r13, #8 @ reserved a couple spots in abort stack
  280. str lr, [r13] @ save caller lr in position 0 of saved stack
  281. mrs lr, spsr @ get the spsr
  282. str lr, [r13, #4] @ save spsr in position 1 of saved stack
  283. mov r13, #MODE_SVC @ prepare SVC-Mode
  284. @ msr spsr_c, r13
  285. msr spsr, r13 @ switch modes, make sure moves will execute
  286. mov lr, pc @ capture return pc
  287. movs pc, lr @ jump to next instruction & switch modes.
  288. .endm
  289. .macro get_irq_stack @ setup IRQ stack
  290. ldr sp, IRQ_STACK_START
  291. .endm
  292. .macro get_fiq_stack @ setup FIQ stack
  293. ldr sp, FIQ_STACK_START
  294. .endm
  295. /*
  296. * exception handlers
  297. */
  298. .align 5
  299. undefined_instruction:
  300. get_bad_stack
  301. bad_save_user_regs
  302. bl do_undefined_instruction
  303. .align 5
  304. software_interrupt:
  305. get_bad_stack
  306. bad_save_user_regs
  307. bl do_software_interrupt
  308. .align 5
  309. prefetch_abort:
  310. get_bad_stack
  311. bad_save_user_regs
  312. bl do_prefetch_abort
  313. .align 5
  314. data_abort:
  315. get_bad_stack
  316. bad_save_user_regs
  317. bl do_data_abort
  318. .align 5
  319. not_used:
  320. get_bad_stack
  321. bad_save_user_regs
  322. bl do_not_used
  323. #ifdef CONFIG_USE_IRQ
  324. .align 5
  325. irq:
  326. get_irq_stack
  327. irq_save_user_regs
  328. bl do_irq
  329. irq_restore_user_regs
  330. .align 5
  331. fiq:
  332. get_fiq_stack
  333. /* someone ought to write a more effiction fiq_save_user_regs */
  334. irq_save_user_regs
  335. bl do_fiq
  336. irq_restore_user_regs
  337. #else
  338. .align 5
  339. irq:
  340. get_bad_stack
  341. bad_save_user_regs
  342. bl do_irq
  343. .align 5
  344. fiq:
  345. get_bad_stack
  346. bad_save_user_regs
  347. bl do_fiq
  348. #endif
  349. .align 5
  350. .globl reset_cpu
  351. reset_cpu:
  352. ldr r1, rstctl1 /* get clkm1 reset ctl */
  353. mov r3, #0x0
  354. strh r3, [r1] /* clear it */
  355. mov r3, #0x8
  356. strh r3, [r1] /* force dsp+arm reset */
  357. _loop_forever:
  358. b _loop_forever
  359. rstctl1:
  360. .word 0xfffece10