pci.c 12 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * (C) Copyright 2002, 2003
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * PCI routines
  28. */
  29. #include <common.h>
  30. #ifdef CONFIG_PCI
  31. #include <command.h>
  32. #include <cmd_boot.h>
  33. #include <asm/processor.h>
  34. #include <asm/io.h>
  35. #include <pci.h>
  36. #ifdef DEBUG
  37. #define DEBUGF(x...) printf(x)
  38. #else
  39. #define DEBUGF(x...)
  40. #endif /* DEBUG */
  41. /*
  42. *
  43. */
  44. #define PCI_HOSE_OP(rw, size, type) \
  45. int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
  46. pci_dev_t dev, \
  47. int offset, type value) \
  48. { \
  49. return hose->rw##_##size(hose, dev, offset, value); \
  50. }
  51. PCI_HOSE_OP(read, byte, u8 *)
  52. PCI_HOSE_OP(read, word, u16 *)
  53. PCI_HOSE_OP(read, dword, u32 *)
  54. PCI_HOSE_OP(write, byte, u8)
  55. PCI_HOSE_OP(write, word, u16)
  56. PCI_HOSE_OP(write, dword, u32)
  57. #define PCI_OP(rw, size, type, error_code) \
  58. int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
  59. { \
  60. struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
  61. \
  62. if (!hose) \
  63. { \
  64. error_code; \
  65. return -1; \
  66. } \
  67. \
  68. return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  69. }
  70. PCI_OP(read, byte, u8 *, *value = 0xff)
  71. PCI_OP(read, word, u16 *, *value = 0xffff)
  72. PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  73. PCI_OP(write, byte, u8, )
  74. PCI_OP(write, word, u16, )
  75. PCI_OP(write, dword, u32, )
  76. #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
  77. int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  78. pci_dev_t dev, \
  79. int offset, type val) \
  80. { \
  81. u32 val32; \
  82. \
  83. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  84. return -1; \
  85. \
  86. *val = (val32 >> ((offset & (int)off_mask) * 8)); \
  87. \
  88. return 0; \
  89. }
  90. #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
  91. int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  92. pci_dev_t dev, \
  93. int offset, type val) \
  94. { \
  95. u32 val32, mask, ldata; \
  96. \
  97. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  98. return -1; \
  99. \
  100. mask = val_mask; \
  101. ldata = (((unsigned long)val) & mask) << ((offset & (int)off_mask) * 8);\
  102. mask <<= ((mask & (int)off_mask) * 8); \
  103. val32 = (val32 & ~mask) | ldata; \
  104. \
  105. if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
  106. return -1; \
  107. \
  108. return 0; \
  109. }
  110. PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
  111. PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
  112. PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
  113. PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
  114. /*
  115. *
  116. */
  117. static struct pci_controller* hose_head = NULL;
  118. void pci_register_hose(struct pci_controller* hose)
  119. {
  120. struct pci_controller **phose = &hose_head;
  121. while(*phose)
  122. phose = &(*phose)->next;
  123. hose->next = NULL;
  124. *phose = hose;
  125. }
  126. struct pci_controller *pci_bus_to_hose (int bus)
  127. {
  128. struct pci_controller *hose;
  129. for (hose = hose_head; hose; hose = hose->next)
  130. if (bus >= hose->first_busno && bus <= hose->last_busno)
  131. return hose;
  132. return NULL;
  133. }
  134. pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
  135. {
  136. struct pci_controller * hose;
  137. u16 vendor, device;
  138. u8 header_type;
  139. pci_dev_t bdf;
  140. int i, bus, found_multi = 0;
  141. for (hose = hose_head; hose; hose = hose->next)
  142. {
  143. #if CFG_SCSI_SCAN_BUS_REVERSE
  144. for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
  145. #else
  146. for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
  147. #endif
  148. for (bdf = PCI_BDF(bus,0,0);
  149. #ifdef CONFIG_ELPPC
  150. bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
  151. #else
  152. bdf < PCI_BDF(bus+1,0,0);
  153. #endif
  154. bdf += PCI_BDF(0,0,1))
  155. {
  156. if (!PCI_FUNC(bdf)) {
  157. pci_read_config_byte(bdf,
  158. PCI_HEADER_TYPE,
  159. &header_type);
  160. found_multi = header_type & 0x80;
  161. } else {
  162. if (!found_multi)
  163. continue;
  164. }
  165. pci_read_config_word(bdf,
  166. PCI_VENDOR_ID,
  167. &vendor);
  168. pci_read_config_word(bdf,
  169. PCI_DEVICE_ID,
  170. &device);
  171. for (i=0; ids[i].vendor != 0; i++)
  172. if (vendor == ids[i].vendor &&
  173. device == ids[i].device)
  174. {
  175. if (index <= 0)
  176. return bdf;
  177. index--;
  178. }
  179. }
  180. }
  181. return (-1);
  182. }
  183. pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
  184. {
  185. static struct pci_device_id ids[2] = {{}, {0, 0}};
  186. ids[0].vendor = vendor;
  187. ids[0].device = device;
  188. return pci_find_devices(ids, index);
  189. }
  190. /*
  191. *
  192. */
  193. unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
  194. unsigned long phys_addr,
  195. unsigned long flags)
  196. {
  197. struct pci_region *res;
  198. unsigned long bus_addr;
  199. int i;
  200. if (!hose) {
  201. printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
  202. goto Done;
  203. }
  204. for (i = 0; i < hose->region_count; i++) {
  205. res = &hose->regions[i];
  206. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  207. continue;
  208. bus_addr = phys_addr - res->phys_start + res->bus_start;
  209. if (bus_addr >= res->bus_start &&
  210. bus_addr < res->bus_start + res->size) {
  211. return bus_addr;
  212. }
  213. }
  214. printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
  215. Done:
  216. return 0;
  217. }
  218. unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
  219. unsigned long bus_addr,
  220. unsigned long flags)
  221. {
  222. struct pci_region *res;
  223. int i;
  224. if (!hose) {
  225. printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
  226. goto Done;
  227. }
  228. for (i = 0; i < hose->region_count; i++) {
  229. res = &hose->regions[i];
  230. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  231. continue;
  232. if (bus_addr >= res->bus_start &&
  233. bus_addr < res->bus_start + res->size) {
  234. return bus_addr - res->bus_start + res->phys_start;
  235. }
  236. }
  237. printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
  238. Done:
  239. return 0;
  240. }
  241. /*
  242. *
  243. */
  244. int pci_hose_config_device(struct pci_controller *hose,
  245. pci_dev_t dev,
  246. unsigned long io,
  247. unsigned long mem,
  248. unsigned long command)
  249. {
  250. unsigned int bar_response, bar_size, bar_value, old_command;
  251. unsigned char pin;
  252. int bar, found_mem64;
  253. DEBUGF ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
  254. io, mem, command);
  255. pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
  256. for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
  257. pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
  258. pci_hose_read_config_dword (hose, dev, bar, &bar_response);
  259. if (!bar_response)
  260. continue;
  261. found_mem64 = 0;
  262. /* Check the BAR type and set our address mask */
  263. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  264. bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
  265. /* round up region base address to a multiple of size */
  266. io = ((io - 1) | (bar_size - 1)) + 1;
  267. bar_value = io;
  268. /* compute new region base address */
  269. io = io + bar_size;
  270. } else {
  271. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  272. PCI_BASE_ADDRESS_MEM_TYPE_64)
  273. found_mem64 = 1;
  274. bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  275. /* round up region base address to multiple of size */
  276. mem = ((mem - 1) | (bar_size - 1)) + 1;
  277. bar_value = mem;
  278. /* compute new region base address */
  279. mem = mem + bar_size;
  280. }
  281. /* Write it out and update our limit */
  282. pci_hose_write_config_dword (hose, dev, bar, bar_value);
  283. if (found_mem64) {
  284. bar += 4;
  285. pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
  286. }
  287. }
  288. /* Configure Cache Line Size Register */
  289. pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  290. /* Configure Latency Timer */
  291. pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
  292. /* Disable interrupt line, if device says it wants to use interrupts */
  293. pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
  294. if (pin != 0) {
  295. pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
  296. }
  297. pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
  298. pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
  299. (old_command & 0xffff0000) | command);
  300. return 0;
  301. }
  302. /*
  303. *
  304. */
  305. struct pci_config_table *pci_find_config(struct pci_controller *hose,
  306. unsigned short class,
  307. unsigned int vendor,
  308. unsigned int device,
  309. unsigned int bus,
  310. unsigned int dev,
  311. unsigned int func)
  312. {
  313. struct pci_config_table *table;
  314. for (table = hose->config_table; table && table->vendor; table++) {
  315. if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
  316. (table->device == PCI_ANY_ID || table->device == device) &&
  317. (table->class == PCI_ANY_ID || table->class == class) &&
  318. (table->bus == PCI_ANY_ID || table->bus == bus) &&
  319. (table->dev == PCI_ANY_ID || table->dev == dev) &&
  320. (table->func == PCI_ANY_ID || table->func == func)) {
  321. return table;
  322. }
  323. }
  324. return NULL;
  325. }
  326. void pci_cfgfunc_config_device(struct pci_controller *hose,
  327. pci_dev_t dev,
  328. struct pci_config_table *entry)
  329. {
  330. pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
  331. }
  332. void pci_cfgfunc_do_nothing(struct pci_controller *hose,
  333. pci_dev_t dev, struct pci_config_table *entry)
  334. {
  335. }
  336. /*
  337. *
  338. */
  339. /* HJF: Changed this to return int. I think this is required
  340. * to get the correct result when scanning bridges
  341. */
  342. extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  343. extern void pciauto_config_init(struct pci_controller *hose);
  344. int pci_hose_scan_bus(struct pci_controller *hose, int bus)
  345. {
  346. unsigned int sub_bus, found_multi=0;
  347. unsigned short vendor, device, class;
  348. unsigned char header_type;
  349. struct pci_config_table *cfg;
  350. pci_dev_t dev;
  351. sub_bus = bus;
  352. for (dev = PCI_BDF(bus,0,0);
  353. dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
  354. dev += PCI_BDF(0,0,1))
  355. {
  356. #ifndef CONFIG_405GP /* don't skip host bridge on ppc405gp */
  357. /* Skip our host bridge */
  358. if ( dev == PCI_BDF(hose->first_busno,0,0) )
  359. continue;
  360. #endif
  361. if (PCI_FUNC(dev) && !found_multi)
  362. continue;
  363. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
  364. pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
  365. if (vendor != 0xffff && vendor != 0x0000) {
  366. if (!PCI_FUNC(dev))
  367. found_multi = header_type & 0x80;
  368. DEBUGF("PCI Scan: Found Bus %d, Device %d, Function %d\n",
  369. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
  370. pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
  371. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  372. cfg = pci_find_config(hose, class, vendor, device,
  373. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  374. if (cfg) {
  375. cfg->config_device(hose, dev, cfg);
  376. #ifdef CONFIG_PCI_PNP
  377. } else {
  378. int n = pciauto_config_device(hose, dev);
  379. sub_bus = max(sub_bus, n);
  380. #endif
  381. }
  382. if (hose->fixup_irq)
  383. hose->fixup_irq(hose, dev);
  384. #ifdef CONFIG_PCI_SCAN_SHOW
  385. /* Skip our host bridge */
  386. if ( dev != PCI_BDF(hose->first_busno,0,0) ) {
  387. unsigned char int_line;
  388. pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
  389. &int_line);
  390. printf(" %02x %02x %04x %04x %04x %02x\n",
  391. PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
  392. int_line);
  393. }
  394. #endif
  395. }
  396. }
  397. return sub_bus;
  398. }
  399. int pci_hose_scan(struct pci_controller *hose)
  400. {
  401. #ifdef CONFIG_PCI_PNP
  402. pciauto_config_init(hose);
  403. #endif
  404. return pci_hose_scan_bus(hose, hose->first_busno);
  405. }
  406. void pci_init(void)
  407. {
  408. #if defined(CONFIG_PCI_BOOTDELAY)
  409. char *s;
  410. int i;
  411. /* wait "pcidelay" ms (if defined)... */
  412. s = getenv ("pcidelay");
  413. if (s) {
  414. int val = simple_strtoul (s, NULL, 10);
  415. for (i=0; i<val; i++)
  416. udelay (1000);
  417. }
  418. #endif /* CONFIG_PCI_BOOTDELAY */
  419. /* now call board specific pci_init()... */
  420. pci_init_board();
  421. }
  422. #endif /* CONFIG_PCI */