i82365.c 15 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. ********************************************************************
  24. *
  25. * Lots of code copied from:
  26. *
  27. * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
  28. * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
  29. * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
  30. */
  31. #include <common.h>
  32. #ifdef CONFIG_I82365
  33. #include <command.h>
  34. #include <pci.h>
  35. #include <pcmcia.h>
  36. #include <cmd_pcmcia.h>
  37. #include <asm/io.h>
  38. #include <pcmcia/ss.h>
  39. #include <pcmcia/i82365.h>
  40. #include <pcmcia/ti113x.h>
  41. #include <pcmcia/yenta.h>
  42. /* #define DEBUG */
  43. static struct pci_device_id supported[] = {
  44. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
  45. {0, 0}
  46. };
  47. #define CYCLE_TIME 120
  48. #ifdef DEBUG
  49. static void i82365_dump_regions (pci_dev_t dev);
  50. #endif
  51. typedef struct socket_info_t {
  52. pci_dev_t dev;
  53. u_short bcr;
  54. u_char pci_lat, cb_lat, sub_bus, cache;
  55. u_int cb_phys;
  56. socket_cap_t cap;
  57. ti113x_state_t state;
  58. } socket_info_t;
  59. static socket_info_t socket;
  60. static socket_state_t state;
  61. static struct pccard_mem_map mem;
  62. static struct pccard_io_map io;
  63. /*====================================================================*/
  64. /* Some PCI shortcuts */
  65. static int pci_readb (socket_info_t * s, int r, u_char * v)
  66. {
  67. return pci_read_config_byte (s->dev, r, v);
  68. }
  69. static int pci_writeb (socket_info_t * s, int r, u_char v)
  70. {
  71. return pci_write_config_byte (s->dev, r, v);
  72. }
  73. static int pci_readw (socket_info_t * s, int r, u_short * v)
  74. {
  75. return pci_read_config_word (s->dev, r, v);
  76. }
  77. static int pci_writew (socket_info_t * s, int r, u_short v)
  78. {
  79. return pci_write_config_word (s->dev, r, v);
  80. }
  81. static int pci_readl (socket_info_t * s, int r, u_int * v)
  82. {
  83. return pci_read_config_dword (s->dev, r, v);
  84. }
  85. static int pci_writel (socket_info_t * s, int r, u_int v)
  86. {
  87. return pci_write_config_dword (s->dev, r, v);
  88. }
  89. #define cb_readb(s, r) readb((s)->cb_phys + (r))
  90. #define cb_readl(s, r) readl((s)->cb_phys + (r))
  91. #define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
  92. #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
  93. /*====================================================================*/
  94. static u_char i365_get (socket_info_t * s, u_short reg)
  95. {
  96. return cb_readb (s, 0x0800 + reg);
  97. }
  98. static void i365_set (socket_info_t * s, u_short reg, u_char data)
  99. {
  100. cb_writeb (s, 0x0800 + reg, data);
  101. }
  102. static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
  103. {
  104. i365_set (s, reg, i365_get (s, reg) | mask);
  105. }
  106. static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
  107. {
  108. i365_set (s, reg, i365_get (s, reg) & ~mask);
  109. }
  110. #if 0 /* not used */
  111. static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
  112. {
  113. u_char d = i365_get (s, reg);
  114. i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
  115. }
  116. static u_short i365_get_pair (socket_info_t * s, u_short reg)
  117. {
  118. return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
  119. }
  120. #endif /* not used */
  121. static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
  122. {
  123. i365_set (s, reg, data & 0xff);
  124. i365_set (s, reg + 1, data >> 8);
  125. }
  126. /*======================================================================
  127. Code to save and restore global state information for TI 1130 and
  128. TI 1131 controllers, and to set and report global configuration
  129. options.
  130. ======================================================================*/
  131. static void ti113x_get_state (socket_info_t * s)
  132. {
  133. ti113x_state_t *p = &s->state;
  134. pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
  135. pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
  136. pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
  137. pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
  138. pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
  139. }
  140. static void ti113x_set_state (socket_info_t * s)
  141. {
  142. ti113x_state_t *p = &s->state;
  143. pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
  144. pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
  145. pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
  146. pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
  147. pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
  148. pci_writel (s, TI12XX_IRQMUX, p->irqmux);
  149. i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
  150. i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
  151. }
  152. static u_int ti113x_set_opts (socket_info_t * s)
  153. {
  154. ti113x_state_t *p = &s->state;
  155. u_int mask = 0xffff;
  156. p->cardctl &= ~TI113X_CCR_ZVENABLE;
  157. p->cardctl |= TI113X_CCR_SPKROUTEN;
  158. return mask;
  159. }
  160. /*======================================================================
  161. Routines to handle common CardBus options
  162. ======================================================================*/
  163. /* Default settings for PCI command configuration register */
  164. #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
  165. PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
  166. static void cb_get_state (socket_info_t * s)
  167. {
  168. pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
  169. pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
  170. pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
  171. pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
  172. pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
  173. pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
  174. }
  175. static void cb_set_state (socket_info_t * s)
  176. {
  177. pci_writel (s, CB_LEGACY_MODE_BASE, 0);
  178. pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
  179. pci_writew (s, PCI_COMMAND, CMD_DFLT);
  180. pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
  181. pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
  182. pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
  183. pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
  184. pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
  185. pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
  186. }
  187. static void cb_set_opts (socket_info_t * s)
  188. {
  189. if (s->cache == 0)
  190. s->cache = 8;
  191. if (s->pci_lat == 0)
  192. s->pci_lat = 0xa8;
  193. if (s->cb_lat == 0)
  194. s->cb_lat = 0xb0;
  195. }
  196. /*======================================================================
  197. Power control for Cardbus controllers: used both for 16-bit and
  198. Cardbus cards.
  199. ======================================================================*/
  200. static int cb_set_power (socket_info_t * s, socket_state_t * state)
  201. {
  202. u_int reg = 0;
  203. /* restart card voltage detection if it seems appropriate */
  204. if ((state->Vcc == 0) && (state->Vpp == 0) &&
  205. !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
  206. cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
  207. switch (state->Vcc) {
  208. case 0:
  209. reg = 0;
  210. break;
  211. case 33:
  212. reg = CB_SC_VCC_3V;
  213. break;
  214. case 50:
  215. reg = CB_SC_VCC_5V;
  216. break;
  217. default:
  218. return -1;
  219. }
  220. switch (state->Vpp) {
  221. case 0:
  222. break;
  223. case 33:
  224. reg |= CB_SC_VPP_3V;
  225. break;
  226. case 50:
  227. reg |= CB_SC_VPP_5V;
  228. break;
  229. case 120:
  230. reg |= CB_SC_VPP_12V;
  231. break;
  232. default:
  233. return -1;
  234. }
  235. if (reg != cb_readl (s, CB_SOCKET_CONTROL))
  236. cb_writel (s, CB_SOCKET_CONTROL, reg);
  237. return 0;
  238. }
  239. /*======================================================================
  240. Generic routines to get and set controller options
  241. ======================================================================*/
  242. static void get_bridge_state (socket_info_t * s)
  243. {
  244. ti113x_get_state (s);
  245. cb_get_state (s);
  246. }
  247. static void set_bridge_state (socket_info_t * s)
  248. {
  249. cb_set_state (s);
  250. i365_set (s, I365_GBLCTL, 0x00);
  251. i365_set (s, I365_GENCTL, 0x00);
  252. ti113x_set_state (s);
  253. }
  254. static void set_bridge_opts (socket_info_t * s)
  255. {
  256. ti113x_set_opts (s);
  257. cb_set_opts (s);
  258. }
  259. /*====================================================================*/
  260. static int i365_get_status (socket_info_t * s, u_int * value)
  261. {
  262. u_int status;
  263. status = i365_get (s, I365_STATUS);
  264. *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
  265. if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
  266. *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
  267. } else {
  268. *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
  269. *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
  270. }
  271. *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
  272. *value |= (status & I365_CS_READY) ? SS_READY : 0;
  273. *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
  274. status = cb_readl (s, CB_SOCKET_STATE);
  275. *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
  276. *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
  277. *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
  278. *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
  279. /* For now, ignore cards with unsupported voltage keys */
  280. if (*value & SS_XVCARD)
  281. *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
  282. return 0;
  283. } /* i365_get_status */
  284. static int i365_set_socket (socket_info_t * s, socket_state_t * state)
  285. {
  286. u_char reg;
  287. set_bridge_state (s);
  288. /* IO card, RESET flag */
  289. reg = 0;
  290. reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
  291. reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
  292. i365_set (s, I365_INTCTL, reg);
  293. reg = I365_PWR_NORESET;
  294. if (state->flags & SS_PWR_AUTO)
  295. reg |= I365_PWR_AUTO;
  296. if (state->flags & SS_OUTPUT_ENA)
  297. reg |= I365_PWR_OUT;
  298. cb_set_power (s, state);
  299. reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
  300. if (reg != i365_get (s, I365_POWER))
  301. i365_set (s, I365_POWER, reg);
  302. return 0;
  303. } /* i365_set_socket */
  304. /*====================================================================*/
  305. static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
  306. {
  307. u_short base, i;
  308. u_char map;
  309. map = mem->map;
  310. if ((map > 4) ||
  311. (mem->card_start > 0x3ffffff) ||
  312. (mem->sys_start > mem->sys_stop) ||
  313. (mem->speed > 1000)) {
  314. return -1;
  315. }
  316. /* Turn off the window before changing anything */
  317. if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
  318. i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
  319. /* Take care of high byte, for PCI controllers */
  320. i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
  321. base = I365_MEM (map);
  322. i = (mem->sys_start >> 12) & 0x0fff;
  323. if (mem->flags & MAP_16BIT)
  324. i |= I365_MEM_16BIT;
  325. if (mem->flags & MAP_0WS)
  326. i |= I365_MEM_0WS;
  327. i365_set_pair (s, base + I365_W_START, i);
  328. i = (mem->sys_stop >> 12) & 0x0fff;
  329. switch (mem->speed / CYCLE_TIME) {
  330. case 0:
  331. break;
  332. case 1:
  333. i |= I365_MEM_WS0;
  334. break;
  335. case 2:
  336. i |= I365_MEM_WS1;
  337. break;
  338. default:
  339. i |= I365_MEM_WS1 | I365_MEM_WS0;
  340. break;
  341. }
  342. i365_set_pair (s, base + I365_W_STOP, i);
  343. i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
  344. if (mem->flags & MAP_WRPROT)
  345. i |= I365_MEM_WRPROT;
  346. if (mem->flags & MAP_ATTRIB)
  347. i |= I365_MEM_REG;
  348. i365_set_pair (s, base + I365_W_OFF, i);
  349. /* Turn on the window if necessary */
  350. if (mem->flags & MAP_ACTIVE)
  351. i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
  352. return 0;
  353. } /* i365_set_mem_map */
  354. static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
  355. {
  356. u_char map, ioctl;
  357. map = io->map;
  358. if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
  359. (io->stop < io->start))
  360. return -1;
  361. /* Turn off the window before changing anything */
  362. if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
  363. i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
  364. i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
  365. i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
  366. ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
  367. if (io->speed)
  368. ioctl |= I365_IOCTL_WAIT (map);
  369. if (io->flags & MAP_0WS)
  370. ioctl |= I365_IOCTL_0WS (map);
  371. if (io->flags & MAP_16BIT)
  372. ioctl |= I365_IOCTL_16BIT (map);
  373. if (io->flags & MAP_AUTOSZ)
  374. ioctl |= I365_IOCTL_IOCS16 (map);
  375. i365_set (s, I365_IOCTL, ioctl);
  376. /* Turn on the window if necessary */
  377. if (io->flags & MAP_ACTIVE)
  378. i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
  379. return 0;
  380. } /* i365_set_io_map */
  381. /*====================================================================*/
  382. int i82365_init (void)
  383. {
  384. u_int val;
  385. int i;
  386. if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
  387. /* Controller not found */
  388. return 1;
  389. }
  390. pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
  391. socket.cb_phys &= ~0xf;
  392. get_bridge_state (&socket);
  393. set_bridge_opts (&socket);
  394. i365_get_status (&socket, &val);
  395. if (val & SS_DETECT) {
  396. if (val & SS_3VCARD) {
  397. state.Vcc = state.Vpp = 33;
  398. puts (" 3.3V card found: ");
  399. } else if (!(val & SS_XVCARD)) {
  400. state.Vcc = state.Vpp = 50;
  401. puts (" 5.0V card found: ");
  402. } else {
  403. printf ("i82365: unsupported voltage key\n");
  404. state.Vcc = state.Vpp = 0;
  405. }
  406. } else {
  407. /* No card inserted */
  408. return 1;
  409. }
  410. state.flags = SS_IOCARD | SS_OUTPUT_ENA;
  411. state.csc_mask = 0;
  412. state.io_irq = 0;
  413. i365_set_socket (&socket, &state);
  414. for (i = 500; i; i--) {
  415. if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
  416. break;
  417. udelay (1000);
  418. }
  419. if (i == 0) {
  420. /* PC Card not ready for data transfer */
  421. return 1;
  422. }
  423. mem.map = 0;
  424. mem.flags = MAP_ATTRIB | MAP_ACTIVE;
  425. mem.speed = 300;
  426. mem.sys_start = CFG_PCMCIA_MEM_ADDR;
  427. mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
  428. mem.card_start = 0;
  429. i365_set_mem_map (&socket, &mem);
  430. io.map = 0;
  431. io.flags = MAP_AUTOSZ | MAP_ACTIVE;
  432. io.speed = 0;
  433. io.start = 0x0100;
  434. io.stop = 0x010F;
  435. i365_set_io_map (&socket, &io);
  436. #ifdef DEBUG
  437. i82365_dump_regions (socket.dev);
  438. #endif
  439. return 0;
  440. }
  441. void i82365_exit (void)
  442. {
  443. io.map = 0;
  444. io.flags = 0;
  445. io.speed = 0;
  446. io.start = 0;
  447. io.stop = 0x1;
  448. i365_set_io_map (&socket, &io);
  449. mem.map = 0;
  450. mem.flags = 0;
  451. mem.speed = 0;
  452. mem.sys_start = 0;
  453. mem.sys_stop = 0x1000;
  454. mem.card_start = 0;
  455. i365_set_mem_map (&socket, &mem);
  456. socket.state.sysctl &= 0xFFFF00FF;
  457. state.Vcc = state.Vpp = 0;
  458. i365_set_socket (&socket, &state);
  459. }
  460. /*======================================================================
  461. Debug stuff
  462. ======================================================================*/
  463. #ifdef DEBUG
  464. static void i82365_dump_regions (pci_dev_t dev)
  465. {
  466. u_int tmp[2];
  467. u_int *mem = (void *) sock.cb_phys;
  468. u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
  469. u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
  470. pci_read_config_dword (dev, 0x00, tmp + 0);
  471. pci_read_config_dword (dev, 0x80, tmp + 1);
  472. printf ("PCI CONF: %08X ... %08X\n", tmp[0], tmp[1]);
  473. printf ("PCI MEM: ... %08X ... %08X\n", mem[0x8 / 4], mem[0x800 / 4]);
  474. printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
  475. cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
  476. cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
  477. printf ("CIS CONF: %02X %02X %02X ...\n",
  478. cis[0x200], cis[0x202], cis[0x204]);
  479. printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
  480. ide[0], ide[1], ide[2], ide[3],
  481. ide[4], ide[5], ide[6], ide[7]);
  482. }
  483. #endif /* DEBUG */
  484. #endif /* CONFIG_I82365 */