cpu.c 4.2 KB

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  1. /*
  2. * Copyright 2004 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. * Change log:
  23. *
  24. * 20050101: Eran Liberty (liberty@freescale.com)
  25. * Initial file creating (porting from 85XX & 8260)
  26. */
  27. /*
  28. * CPU specific code for the MPC83xx family.
  29. *
  30. * Derived from the MPC8260 and MPC85xx.
  31. */
  32. #include <common.h>
  33. #include <watchdog.h>
  34. #include <command.h>
  35. #include <mpc83xx.h>
  36. #include <ft_build.h>
  37. #include <asm/processor.h>
  38. int checkcpu(void)
  39. {
  40. DECLARE_GLOBAL_DATA_PTR;
  41. ulong clock = gd->cpu_clk;
  42. u32 pvr = get_pvr();
  43. char buf[32];
  44. if ((pvr & 0xFFFF0000) != PVR_83xx) {
  45. puts("Not MPC83xx Family!!!\n");
  46. return -1;
  47. }
  48. puts("CPU: MPC83xx, ");
  49. switch(pvr) {
  50. case PVR_8349_REV10:
  51. break;
  52. case PVR_8349_REV11:
  53. break;
  54. default:
  55. puts("Rev: Unknown\n");
  56. return -1; /* Not sure what this is */
  57. }
  58. printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
  59. (pvr & 0x0f), strmhz(buf, clock));
  60. return 0;
  61. }
  62. void upmconfig (uint upm, uint *table, uint size)
  63. {
  64. hang(); /* FIXME: upconfig() needed? */
  65. }
  66. int
  67. do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  68. {
  69. ulong msr;
  70. #ifndef MPC83xx_RESET
  71. ulong addr;
  72. #endif
  73. volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
  74. #ifdef MPC83xx_RESET
  75. /* Interrupts and MMU off */
  76. __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
  77. msr &= ~( MSR_EE | MSR_IR | MSR_DR);
  78. __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
  79. /* enable Reset Control Reg */
  80. immap->reset.rpr = 0x52535445;
  81. __asm__ __volatile__ ("sync");
  82. __asm__ __volatile__ ("isync");
  83. /* confirm Reset Control Reg is enabled */
  84. while(!((immap->reset.rcer) & RCER_CRE));
  85. printf("Resetting the board.");
  86. printf("\n");
  87. udelay(200);
  88. /* perform reset, only one bit */
  89. immap->reset.rcr = RCR_SWHR;
  90. #else /* ! MPC83xx_RESET */
  91. immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
  92. /* Interrupts and MMU off */
  93. __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
  94. msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
  95. __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
  96. /*
  97. * Trying to execute the next instruction at a non-existing address
  98. * should cause a machine check, resulting in reset
  99. */
  100. addr = CFG_RESET_ADDRESS;
  101. printf("resetting the board.");
  102. printf("\n");
  103. ((void (*)(void)) addr) ();
  104. #endif /* MPC83xx_RESET */
  105. return 1;
  106. }
  107. /*
  108. * Get timebase clock frequency (like cpu_clk in Hz)
  109. */
  110. unsigned long get_tbclk(void)
  111. {
  112. DECLARE_GLOBAL_DATA_PTR;
  113. ulong tbclk;
  114. tbclk = (gd->bus_clk + 3L) / 4L;
  115. return tbclk;
  116. }
  117. #if defined(CONFIG_WATCHDOG)
  118. void watchdog_reset (void)
  119. {
  120. hang(); /* FIXME: implement watchdog_reset()? */
  121. }
  122. #endif /* CONFIG_WATCHDOG */
  123. #if defined(CONFIG_OF_FLAT_TREE)
  124. void
  125. ft_cpu_setup(void *blob, bd_t *bd)
  126. {
  127. u32 *p;
  128. int len;
  129. ulong clock;
  130. clock = bd->bi_busfreq;
  131. p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
  132. if (p != NULL)
  133. *p = cpu_to_be32(clock);
  134. p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
  135. if (p != NULL)
  136. *p = cpu_to_be32(clock);
  137. p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
  138. if (p != NULL)
  139. *p = cpu_to_be32(clock);
  140. p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
  141. if (p != NULL)
  142. *p = cpu_to_be32(clock);
  143. #ifdef CONFIG_MPC83XX_TSEC1
  144. p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
  145. memcpy(p, bd->bi_enetaddr, 6);
  146. #endif
  147. #ifdef CONFIG_MPC83XX_TSEC2
  148. p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
  149. memcpy(p, bd->bi_enet1addr, 6);
  150. #endif
  151. }
  152. #endif