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include
/
asm-blackfin
/
arch-bf561
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defBF561_extn.h

defBF561_extn.h 2.2 KB
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  1. /*
    2. 

  2.  * defBF561_extn.h
    3. 

  3.  *
    4. 

  4.  * This file is subject to the terms and conditions of the GNU Public
    5. 

  5.  * License. See the file "COPYING" in the main directory of this archive
    6. 

  6.  * for more details.
    7. 

  7.  *
    8. 

  8.  * Non-GPL License also available as part of VisualDSP++
    9. 

  9.  *
    10. 

  10.  * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
    11. 

  11.  *
    12. 

  12.  * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
    13. 

  13.  *
    14. 

  14.  * This file under source code control, please send bugs or changes to:
    15. 

  15.  * dsptools.support@analog.com
    16. 

  16.  *
    17. 

  17.  */
    18. 

  18. 

  19. #ifndef _DEF_BF561_EXTN_H
    20. 

  20. #define _DEF_BF561_EXTN_H
    21. 

  21. 

  22. #define OFFSET_( x )		((x) & 0x0000FFFF) /* define macro for offset */
    23. 

  23. /* Delay inserted for PLL transition */
    24. 

  24. #define PLL_DELAY		0x1000
    25. 

  25. 

  26. #define L1_ISRAM		0xFFA00000
    27. 

  27. #define L1_ISRAM_END		0xFFA10000
    28. 

  28. #define DATA_BANKA_SRAM		0xFF800000
    29. 

  29. #define DATA_BANKA_SRAM_END	0xFF808000
    30. 

  30. #define DATA_BANKB_SRAM		0xFF900000
    31. 

  31. #define DATA_BANKB_SRAM_END	0xFF908000
    32. 

  32. #define SYSMMR_BASE		0xFFC00000
    33. 

  33. #define WDSIZE16		0x00000004
    34. 

  34. 

  35. /* Event Vector Table Address */
    36. 

  36. #define EVT_EMULATION_ADDR	0xffe02000
    37. 

  37. #define EVT_RESET_ADDR		0xffe02004
    38. 

  38. #define EVT_NMI_ADDR		0xffe02008
    39. 

  39. #define EVT_EXCEPTION_ADDR	0xffe0200c
    40. 

  40. #define EVT_GLOBAL_INT_ENB_ADDR	0xffe02010
    41. 

  41. #define EVT_HARDWARE_ERROR_ADDR	0xffe02014
    42. 

  42. #define EVT_TIMER_ADDR		0xffe02018
    43. 

  43. #define EVT_IVG7_ADDR		0xffe0201c
    44. 

  44. #define EVT_IVG8_ADDR		0xffe02020
    45. 

  45. #define EVT_IVG9_ADDR		0xffe02024
    46. 

  46. #define EVT_IVG10_ADDR		0xffe02028
    47. 

  47. #define EVT_IVG11_ADDR		0xffe0202c
    48. 

  48. #define EVT_IVG12_ADDR		0xffe02030
    49. 

  49. #define EVT_IVG13_ADDR		0xffe02034
    50. 

  50. #define EVT_IVG14_ADDR		0xffe02038
    51. 

  51. #define EVT_IVG15_ADDR		0xffe0203c
    52. 

  52. #define EVT_OVERRIDE_ADDR	0xffe02100
    53. 

  53. 

  54. /* IMASK Bit values */
    55. 

  55. #define IVG15_POS		0x00008000
    56. 

  56. #define IVG14_POS		0x00004000
    57. 

  57. #define IVG13_POS		0x00002000
    58. 

  58. #define IVG12_POS		0x00001000
    59. 

  59. #define IVG11_POS		0x00000800
    60. 

  60. #define IVG10_POS		0x00000400
    61. 

  61. #define IVG9_POS		0x00000200
    62. 

  62. #define IVG8_POS		0x00000100
    63. 

  63. #define IVG7_POS		0x00000080
    64. 

  64. #define IVGTMR_POS		0x00000040
    65. 

  65. #define IVGHW_POS		0x00000020
    66. 

  66. 

  67. #define WDOG_TMR_DISABLE	(0xAD << 4)
    68. 

  68. #define ICTL_RST		0x00000000
    69. 

  69. #define ICTL_NMI		0x00000002
    70. 

  70. #define ICTL_GP			0x00000004
    71. 

  71. #define ICTL_DISABLE		0x00000003
    72. 

  72. 

  73. /* Watch Dog timer values setup */
    74. 

  74. #define WATCHDOG_DISABLE	WDOG_TMR_DISABLE | ICTL_DISABLE
    75. 

  75. 

  76. #endif	/* _DEF_BF561_EXTN_H */
    77.