adp-ag101p.h 10.0 KB

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  1. /*
  2. * Copyright (C) 2011 Andes Technology Corporation
  3. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  4. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #ifndef __CONFIG_H
  24. #define __CONFIG_H
  25. #include <asm/arch/ag101.h>
  26. /*
  27. * CPU and Board Configuration Options
  28. */
  29. #define CONFIG_ADP_AG101P
  30. #define CONFIG_USE_INTERRUPT
  31. #define CONFIG_SKIP_LOWLEVEL_INIT
  32. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  33. #define CONFIG_MEM_REMAP
  34. #endif
  35. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  36. #define CONFIG_SYS_TEXT_BASE 0x03200000
  37. #else
  38. #define CONFIG_SYS_TEXT_BASE 0x00000000
  39. #endif
  40. /*
  41. * Timer
  42. */
  43. /*
  44. * According to the discussion in u-boot mailing list before,
  45. * CONFIG_SYS_HZ at 1000 is mandatory.
  46. */
  47. #define CONFIG_SYS_HZ 1000
  48. #define CONFIG_SYS_CLK_FREQ 39062500
  49. #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
  50. /*
  51. * Use Externel CLOCK or PCLK
  52. */
  53. #undef CONFIG_FTRTC010_EXTCLK
  54. #ifndef CONFIG_FTRTC010_EXTCLK
  55. #define CONFIG_FTRTC010_PCLK
  56. #endif
  57. #ifdef CONFIG_FTRTC010_EXTCLK
  58. #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
  59. #else
  60. #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
  61. #endif
  62. #define TIMER_LOAD_VAL 0xffffffff
  63. /*
  64. * Real Time Clock
  65. */
  66. #define CONFIG_RTC_FTRTC010
  67. /*
  68. * Real Time Clock Divider
  69. * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
  70. */
  71. #define OSC_5MHZ (5*1000000)
  72. #define OSC_CLK (4*OSC_5MHZ)
  73. #define RTC_DIV_COUNT (0.5) /* Why?? */
  74. /*
  75. * Serial console configuration
  76. */
  77. /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  78. #define CONFIG_BAUDRATE 38400
  79. #define CONFIG_CONS_INDEX 1
  80. #define CONFIG_SYS_NS16550
  81. #define CONFIG_SYS_NS16550_SERIAL
  82. #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
  83. #define CONFIG_SYS_NS16550_REG_SIZE -4
  84. #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
  85. /* valid baudrates */
  86. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  87. /*
  88. * Ethernet
  89. */
  90. #define CONFIG_FTMAC100
  91. #define CONFIG_BOOTDELAY 3
  92. /*
  93. * SD (MMC) controller
  94. */
  95. #define CONFIG_MMC
  96. #define CONFIG_CMD_MMC
  97. #define CONFIG_GENERIC_MMC
  98. #define CONFIG_DOS_PARTITION
  99. #define CONFIG_FTSDC010
  100. #define CONFIG_FTSDC010_NUMBER 1
  101. #define CONFIG_CMD_FAT
  102. /*
  103. * Command line configuration.
  104. */
  105. #include <config_cmd_default.h>
  106. #define CONFIG_CMD_CACHE
  107. #define CONFIG_CMD_DATE
  108. #define CONFIG_CMD_PING
  109. /*
  110. * Miscellaneous configurable options
  111. */
  112. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  113. #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
  114. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  115. /* Print Buffer Size */
  116. #define CONFIG_SYS_PBSIZE \
  117. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  118. /* max number of command args */
  119. #define CONFIG_SYS_MAXARGS 16
  120. /* Boot Argument Buffer Size */
  121. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  122. /*
  123. * Stack sizes
  124. *
  125. * The stack sizes are set up in start.S using the settings below
  126. */
  127. #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
  128. /*
  129. * Size of malloc() pool
  130. */
  131. /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  132. #define CONFIG_SYS_MALLOC_LEN (512 << 10)
  133. /*
  134. * size in bytes reserved for initial data
  135. */
  136. #define CONFIG_SYS_GBL_DATA_SIZE 128
  137. /*
  138. * AHB Controller configuration
  139. */
  140. #define CONFIG_FTAHBC020S
  141. #ifdef CONFIG_FTAHBC020S
  142. #include <faraday/ftahbc020s.h>
  143. /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  144. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
  145. /*
  146. * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  147. * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  148. * in C language.
  149. */
  150. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
  151. (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
  152. FTAHBC020S_SLAVE_BSR_SIZE(0xb))
  153. #endif
  154. /*
  155. * Watchdog
  156. */
  157. #define CONFIG_FTWDT010_WATCHDOG
  158. /*
  159. * PMU Power controller configuration
  160. */
  161. #define CONFIG_PMU
  162. #define CONFIG_FTPMU010_POWER
  163. #ifdef CONFIG_FTPMU010_POWER
  164. #include <faraday/ftpmu010.h>
  165. #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
  166. #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
  167. FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
  168. FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
  169. FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
  170. FTPMU010_SDRAMHTC_CKE_DCSR | \
  171. FTPMU010_SDRAMHTC_DQM_DCSR | \
  172. FTPMU010_SDRAMHTC_SDCLK_DCSR)
  173. #endif
  174. /*
  175. * SDRAM controller configuration
  176. */
  177. #define CONFIG_FTSDMC021
  178. #ifdef CONFIG_FTSDMC021
  179. #include <faraday/ftsdmc021.h>
  180. #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
  181. FTSDMC021_TP1_TRP(1) | \
  182. FTSDMC021_TP1_TRCD(1) | \
  183. FTSDMC021_TP1_TRF(3) | \
  184. FTSDMC021_TP1_TWR(1) | \
  185. FTSDMC021_TP1_TCL(2))
  186. #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
  187. FTSDMC021_TP2_INI_REFT(8) | \
  188. FTSDMC021_TP2_REF_INTV(0x180))
  189. /*
  190. * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
  191. * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
  192. * C language.
  193. */
  194. #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
  195. FTSDMC021_CR1_DSZ(3) | \
  196. FTSDMC021_CR1_MBW(2) | \
  197. FTSDMC021_CR1_BNKSIZE(6))
  198. #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
  199. FTSDMC021_CR2_IREF | \
  200. FTSDMC021_CR2_ISMR)
  201. #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
  202. #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
  203. CONFIG_SYS_FTSDMC021_BANK0_BASE)
  204. #endif
  205. /*
  206. * Physical Memory Map
  207. */
  208. #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
  209. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  210. #if defined(CONFIG_MEM_REMAP)
  211. #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
  212. #endif
  213. #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
  214. #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
  215. #endif
  216. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  217. #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
  218. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
  219. #ifdef CONFIG_MEM_REMAP
  220. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  221. GENERATED_GBL_DATA_SIZE)
  222. #else
  223. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
  224. GENERATED_GBL_DATA_SIZE)
  225. #endif /* CONFIG_MEM_REMAP */
  226. /*
  227. * Load address and memory test area should agree with
  228. * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
  229. */
  230. #define CONFIG_SYS_LOAD_ADDR 0x300000
  231. /* memtest works on 63 MB in DRAM */
  232. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
  233. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
  234. /*
  235. * Static memory controller configuration
  236. */
  237. #define CONFIG_FTSMC020
  238. #ifdef CONFIG_FTSMC020
  239. #include <faraday/ftsmc020.h>
  240. #define CONFIG_SYS_FTSMC020_CONFIGS { \
  241. { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
  242. { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
  243. }
  244. #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
  245. #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
  246. FTSMC020_BANK_SIZE_32M | \
  247. FTSMC020_BANK_MBW_32)
  248. #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
  249. FTSMC020_TPR_AST(1) | \
  250. FTSMC020_TPR_CTW(1) | \
  251. FTSMC020_TPR_ATI(1) | \
  252. FTSMC020_TPR_AT2(1) | \
  253. FTSMC020_TPR_WTC(1) | \
  254. FTSMC020_TPR_AHT(1) | \
  255. FTSMC020_TPR_TRNA(1))
  256. #endif
  257. /*
  258. * FLASH on ADP_AG101P is connected to BANK0
  259. * Just disalbe the other BANK to avoid detection error.
  260. */
  261. #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
  262. FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
  263. FTSMC020_BANK_SIZE_32M | \
  264. FTSMC020_BANK_MBW_32)
  265. #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
  266. FTSMC020_TPR_CTW(3) | \
  267. FTSMC020_TPR_ATI(0xf) | \
  268. FTSMC020_TPR_AT2(3) | \
  269. FTSMC020_TPR_WTC(3) | \
  270. FTSMC020_TPR_AHT(3) | \
  271. FTSMC020_TPR_TRNA(0xf))
  272. #define FTSMC020_BANK1_CONFIG (0x00)
  273. #define FTSMC020_BANK1_TIMING (0x00)
  274. #endif /* CONFIG_FTSMC020 */
  275. /*
  276. * FLASH and environment organization
  277. */
  278. /* use CFI framework */
  279. #define CONFIG_SYS_FLASH_CFI
  280. #define CONFIG_FLASH_CFI_DRIVER
  281. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  282. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  283. /* support JEDEC */
  284. /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
  285. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  286. #define PHYS_FLASH_1 0x80400000 /* BANK 1 */
  287. #else /* !CONFIG_SKIP_LOWLEVEL_INIT */
  288. #ifdef CONFIG_MEM_REMAP
  289. #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
  290. #else
  291. #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
  292. #endif /* CONFIG_MEM_REMAP */
  293. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  294. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  295. #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
  296. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  297. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
  298. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
  299. /* max number of memory banks */
  300. /*
  301. * There are 4 banks supported for this Controller,
  302. * but we have only 1 bank connected to flash on board
  303. */
  304. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  305. /* max number of sectors on one chip */
  306. #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
  307. #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
  308. #define CONFIG_SYS_MAX_FLASH_SECT 128
  309. /* environments */
  310. #define CONFIG_ENV_IS_IN_FLASH
  311. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
  312. #define CONFIG_ENV_SIZE 8192
  313. #define CONFIG_ENV_OVERWRITE
  314. #endif /* __CONFIG_H */