tegra2-seaboard.dts 1.5 KB

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  1. /dts-v1/;
  2. /memreserve/ 0x1c000000 0x04000000;
  3. /include/ ARCH_CPU_DTS
  4. / {
  5. model = "NVIDIA Seaboard";
  6. compatible = "nvidia,seaboard", "nvidia,tegra20";
  7. chosen {
  8. bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
  9. };
  10. aliases {
  11. /* This defines the order of our USB ports */
  12. usb0 = "/usb@c5008000";
  13. usb1 = "/usb@c5000000";
  14. i2c0 = "/i2c@7000d000";
  15. i2c1 = "/i2c@7000c000";
  16. i2c2 = "/i2c@7000c400";
  17. i2c3 = "/i2c@7000c500";
  18. };
  19. memory {
  20. device_type = "memory";
  21. reg = < 0x00000000 0x40000000 >;
  22. };
  23. /* This is not used in U-Boot, but is expected to be in kernel .dts */
  24. i2c@7000d000 {
  25. clock-frequency = <100000>;
  26. pmic@34 {
  27. compatible = "ti,tps6586x";
  28. reg = <0x34>;
  29. clk_32k: clock {
  30. compatible = "fixed-clock";
  31. /*
  32. * leave out for now due to CPP:
  33. * #clock-cells = <0>;
  34. */
  35. clock-frequency = <32768>;
  36. };
  37. };
  38. };
  39. clocks {
  40. osc {
  41. clock-frequency = <12000000>;
  42. };
  43. };
  44. clock@60006000 {
  45. clocks = <&clk_32k &osc>;
  46. };
  47. serial@70006300 {
  48. clock-frequency = < 216000000 >;
  49. };
  50. sdhci@c8000400 {
  51. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  52. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  53. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  54. };
  55. sdhci@c8000600 {
  56. support-8bit;
  57. };
  58. usb@c5000000 {
  59. nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
  60. dr_mode = "otg";
  61. };
  62. usb@c5004000 {
  63. status = "disabled";
  64. };
  65. i2c@7000c000 {
  66. clock-frequency = <100000>;
  67. };
  68. i2c@7000c400 {
  69. status = "disabled";
  70. };
  71. i2c@7000c500 {
  72. clock-frequency = <100000>;
  73. };
  74. };