start.S 13 KB

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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
  5. * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * File: start.S
  27. *
  28. * Discription: startup code
  29. *
  30. */
  31. #include <asm-offsets.h>
  32. #include <config.h>
  33. #include <mpc5xx.h>
  34. #include <version.h>
  35. #define CONFIG_5xx 1 /* needed for Linux kernel header files */
  36. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  37. #include <ppc_asm.tmpl>
  38. #include <ppc_defs.h>
  39. #include <linux/config.h>
  40. #include <asm/processor.h>
  41. #include <asm/u-boot.h>
  42. /* We don't have a MMU.
  43. */
  44. #undef MSR_KERNEL
  45. #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
  46. /*
  47. * Set up GOT: Global Offset Table
  48. *
  49. * Use r12 to access the GOT
  50. */
  51. START_GOT
  52. GOT_ENTRY(_GOT2_TABLE_)
  53. GOT_ENTRY(_FIXUP_TABLE_)
  54. GOT_ENTRY(_start)
  55. GOT_ENTRY(_start_of_vectors)
  56. GOT_ENTRY(_end_of_vectors)
  57. GOT_ENTRY(transfer_to_handler)
  58. GOT_ENTRY(__init_end)
  59. GOT_ENTRY(__bss_end__)
  60. GOT_ENTRY(__bss_start)
  61. END_GOT
  62. /*
  63. * r3 - 1st arg to board_init(): IMMP pointer
  64. * r4 - 2nd arg to board_init(): boot flag
  65. */
  66. .text
  67. .long 0x27051956 /* U-Boot Magic Number */
  68. .globl version_string
  69. version_string:
  70. .ascii U_BOOT_VERSION_STRING, "\0"
  71. . = EXC_OFF_SYS_RESET
  72. .globl _start
  73. _start:
  74. mfspr r3, 638
  75. li r4, CONFIG_SYS_ISB /* Set ISB bit */
  76. or r3, r3, r4
  77. mtspr 638, r3
  78. /* Initialize machine status; enable machine check interrupt */
  79. /*----------------------------------------------------------------------*/
  80. li r3, MSR_KERNEL /* Set ME, RI flags */
  81. mtmsr r3
  82. mtspr SRR1, r3 /* Make SRR1 match MSR */
  83. /* Initialize debug port registers */
  84. /*----------------------------------------------------------------------*/
  85. xor r0, r0, r0 /* Clear R0 */
  86. mtspr LCTRL1, r0 /* Initialize debug port regs */
  87. mtspr LCTRL2, r0
  88. mtspr COUNTA, r0
  89. mtspr COUNTB, r0
  90. #if defined(CONFIG_PATI)
  91. /* the external flash access on PATI fails if programming the PLL to 40MHz.
  92. * Copy the PLL programming code to the internal RAM and execute it
  93. *----------------------------------------------------------------------*/
  94. lis r3, CONFIG_SYS_MONITOR_BASE@h
  95. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  96. addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
  97. lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
  98. ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
  99. mtlr r4
  100. addis r5,0,0x0
  101. ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
  102. mtctr r5
  103. addi r3, r3, -4
  104. addi r4, r4, -4
  105. 0:
  106. lwzu r0,4(r3)
  107. stwu r0,4(r4)
  108. bdnz 0b /* copy loop */
  109. blrl
  110. #endif
  111. /*
  112. * Calculate absolute address in FLASH and jump there
  113. *----------------------------------------------------------------------*/
  114. lis r3, CONFIG_SYS_MONITOR_BASE@h
  115. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  116. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  117. mtlr r3
  118. blr
  119. in_flash:
  120. /* Initialize some SPRs that are hard to access from C */
  121. /*----------------------------------------------------------------------*/
  122. lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */
  123. lis r2, CONFIG_SYS_INIT_SP_ADDR@h
  124. ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
  125. /* Note: R0 is still 0 here */
  126. stwu r0, -4(r1) /* Clear final stack frame so that */
  127. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  128. /*
  129. * Disable serialized ifetch and show cycles
  130. * (i.e. set processor to normal mode) for maximum
  131. * performance.
  132. */
  133. li r2, 0x0007
  134. mtspr ICTRL, r2
  135. /* Set up debug mode entry */
  136. lis r2, CONFIG_SYS_DER@h
  137. ori r2, r2, CONFIG_SYS_DER@l
  138. mtspr DER, r2
  139. /* Let the C-code set up the rest */
  140. /* */
  141. /* Be careful to keep code relocatable ! */
  142. /*----------------------------------------------------------------------*/
  143. GET_GOT /* initialize GOT access */
  144. /* r3: IMMR */
  145. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  146. bl board_init_f /* run 1st part of board init code (from Flash) */
  147. /* NOTREACHED - board_init_f() does not return */
  148. .globl _start_of_vectors
  149. _start_of_vectors:
  150. /* Machine check */
  151. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  152. /* Data Storage exception. "Never" generated on the 860. */
  153. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  154. /* Instruction Storage exception. "Never" generated on the 860. */
  155. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  156. /* External Interrupt exception. */
  157. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  158. /* Alignment exception. */
  159. . = 0x600
  160. Alignment:
  161. EXCEPTION_PROLOG(SRR0, SRR1)
  162. mfspr r4,DAR
  163. stw r4,_DAR(r21)
  164. mfspr r5,DSISR
  165. stw r5,_DSISR(r21)
  166. addi r3,r1,STACK_FRAME_OVERHEAD
  167. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  168. /* Program check exception */
  169. . = 0x700
  170. ProgramCheck:
  171. EXCEPTION_PROLOG(SRR0, SRR1)
  172. addi r3,r1,STACK_FRAME_OVERHEAD
  173. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  174. MSR_KERNEL, COPY_EE)
  175. /* FPU on MPC5xx available. We will use it later.
  176. */
  177. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  178. /* I guess we could implement decrementer, and may have
  179. * to someday for timekeeping.
  180. */
  181. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  182. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  183. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  184. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  185. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  186. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  187. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  188. /* On the MPC8xx, this is a software emulation interrupt. It occurs
  189. * for all unimplemented and illegal instructions.
  190. */
  191. STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
  192. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  193. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  194. STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
  195. STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
  196. STD_EXCEPTION(0x1500, Reserved5, UnknownException)
  197. STD_EXCEPTION(0x1600, Reserved6, UnknownException)
  198. STD_EXCEPTION(0x1700, Reserved7, UnknownException)
  199. STD_EXCEPTION(0x1800, Reserved8, UnknownException)
  200. STD_EXCEPTION(0x1900, Reserved9, UnknownException)
  201. STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
  202. STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
  203. STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
  204. STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
  205. STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
  206. STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
  207. .globl _end_of_vectors
  208. _end_of_vectors:
  209. . = 0x2000
  210. /*
  211. * This code finishes saving the registers to the exception frame
  212. * and jumps to the appropriate handler for the exception.
  213. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  214. */
  215. .globl transfer_to_handler
  216. transfer_to_handler:
  217. stw r22,_NIP(r21)
  218. lis r22,MSR_POW@h
  219. andc r23,r23,r22
  220. stw r23,_MSR(r21)
  221. SAVE_GPR(7, r21)
  222. SAVE_4GPRS(8, r21)
  223. SAVE_8GPRS(12, r21)
  224. SAVE_8GPRS(24, r21)
  225. mflr r23
  226. andi. r24,r23,0x3f00 /* get vector offset */
  227. stw r24,TRAP(r21)
  228. li r22,0
  229. stw r22,RESULT(r21)
  230. mtspr SPRG2,r22 /* r1 is now kernel sp */
  231. lwz r24,0(r23) /* virtual address of handler */
  232. lwz r23,4(r23) /* where to go when done */
  233. mtspr SRR0,r24
  234. mtspr SRR1,r20
  235. mtlr r23
  236. SYNC
  237. rfi /* jump to handler, enable MMU */
  238. int_return:
  239. mfmsr r28 /* Disable interrupts */
  240. li r4,0
  241. ori r4,r4,MSR_EE
  242. andc r28,r28,r4
  243. SYNC /* Some chip revs need this... */
  244. mtmsr r28
  245. SYNC
  246. lwz r2,_CTR(r1)
  247. lwz r0,_LINK(r1)
  248. mtctr r2
  249. mtlr r0
  250. lwz r2,_XER(r1)
  251. lwz r0,_CCR(r1)
  252. mtspr XER,r2
  253. mtcrf 0xFF,r0
  254. REST_10GPRS(3, r1)
  255. REST_10GPRS(13, r1)
  256. REST_8GPRS(23, r1)
  257. REST_GPR(31, r1)
  258. lwz r2,_NIP(r1) /* Restore environment */
  259. lwz r0,_MSR(r1)
  260. mtspr SRR0,r2
  261. mtspr SRR1,r0
  262. lwz r0,GPR0(r1)
  263. lwz r2,GPR2(r1)
  264. lwz r1,GPR1(r1)
  265. SYNC
  266. rfi
  267. /*
  268. * unsigned int get_immr (unsigned int mask)
  269. *
  270. * return (mask ? (IMMR & mask) : IMMR);
  271. */
  272. .globl get_immr
  273. get_immr:
  274. mr r4,r3 /* save mask */
  275. mfspr r3, IMMR /* IMMR */
  276. cmpwi 0,r4,0 /* mask != 0 ? */
  277. beq 4f
  278. and r3,r3,r4 /* IMMR & mask */
  279. 4:
  280. blr
  281. .globl get_pvr
  282. get_pvr:
  283. mfspr r3, PVR
  284. blr
  285. /*------------------------------------------------------------------------------*/
  286. /*
  287. * void relocate_code (addr_sp, gd, addr_moni)
  288. *
  289. * This "function" does not return, instead it continues in RAM
  290. * after relocating the monitor code.
  291. *
  292. * r3 = dest
  293. * r4 = src
  294. * r5 = length in bytes
  295. * r6 = cachelinesize
  296. */
  297. .globl relocate_code
  298. relocate_code:
  299. mr r1, r3 /* Set new stack pointer in SRAM */
  300. mr r9, r4 /* Save copy of global data pointer in SRAM */
  301. mr r10, r5 /* Save copy of monitor destination Address in SRAM */
  302. GET_GOT
  303. mr r3, r5 /* Destination Address */
  304. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  305. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  306. lwz r5, GOT(__init_end)
  307. sub r5, r5, r4
  308. /*
  309. * Fix GOT pointer:
  310. *
  311. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  312. *
  313. * Offset:
  314. */
  315. sub r15, r10, r4
  316. /* First our own GOT */
  317. add r12, r12, r15
  318. /* the the one used by the C code */
  319. add r30, r30, r15
  320. /*
  321. * Now relocate code
  322. */
  323. cmplw cr1,r3,r4
  324. addi r0,r5,3
  325. srwi. r0,r0,2
  326. beq cr1,4f /* In place copy is not necessary */
  327. beq 4f /* Protect against 0 count */
  328. mtctr r0
  329. bge cr1,2f
  330. la r8,-4(r4)
  331. la r7,-4(r3)
  332. 1: lwzu r0,4(r8)
  333. stwu r0,4(r7)
  334. bdnz 1b
  335. b 4f
  336. 2: slwi r0,r0,2
  337. add r8,r4,r0
  338. add r7,r3,r0
  339. 3: lwzu r0,-4(r8)
  340. stwu r0,-4(r7)
  341. bdnz 3b
  342. 4: sync
  343. isync
  344. /*
  345. * We are done. Do not return, instead branch to second part of board
  346. * initialization, now running from RAM.
  347. */
  348. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  349. mtlr r0
  350. blr
  351. in_ram:
  352. /*
  353. * Relocation Function, r12 point to got2+0x8000
  354. *
  355. * Adjust got2 pointers, no need to check for 0, this code
  356. * already puts a few entries in the table.
  357. */
  358. li r0,__got2_entries@sectoff@l
  359. la r3,GOT(_GOT2_TABLE_)
  360. lwz r11,GOT(_GOT2_TABLE_)
  361. mtctr r0
  362. sub r11,r3,r11
  363. addi r3,r3,-4
  364. 1: lwzu r0,4(r3)
  365. cmpwi r0,0
  366. beq- 2f
  367. add r0,r0,r11
  368. stw r0,0(r3)
  369. 2: bdnz 1b
  370. /*
  371. * Now adjust the fixups and the pointers to the fixups
  372. * in case we need to move ourselves again.
  373. */
  374. li r0,__fixup_entries@sectoff@l
  375. lwz r3,GOT(_FIXUP_TABLE_)
  376. cmpwi r0,0
  377. mtctr r0
  378. addi r3,r3,-4
  379. beq 4f
  380. 3: lwzu r4,4(r3)
  381. lwzux r0,r4,r11
  382. cmpwi r0,0
  383. add r0,r0,r11
  384. stw r4,0(r3)
  385. beq- 5f
  386. stw r0,0(r4)
  387. 5: bdnz 3b
  388. 4:
  389. clear_bss:
  390. /*
  391. * Now clear BSS segment
  392. */
  393. lwz r3,GOT(__bss_start)
  394. lwz r4,GOT(__bss_end__)
  395. cmplw 0, r3, r4
  396. beq 6f
  397. li r0, 0
  398. 5:
  399. stw r0, 0(r3)
  400. addi r3, r3, 4
  401. cmplw 0, r3, r4
  402. bne 5b
  403. 6:
  404. mr r3, r9 /* Global Data pointer */
  405. mr r4, r10 /* Destination Address */
  406. bl board_init_r
  407. /*
  408. * Copy exception vector code to low memory
  409. *
  410. * r3: dest_addr
  411. * r7: source address, r8: end address, r9: target address
  412. */
  413. .globl trap_init
  414. trap_init:
  415. mflr r4 /* save link register */
  416. GET_GOT
  417. lwz r7, GOT(_start)
  418. lwz r8, GOT(_end_of_vectors)
  419. li r9, 0x100 /* reset vector always at 0x100 */
  420. cmplw 0, r7, r8
  421. bgelr /* return if r7>=r8 - just in case */
  422. 1:
  423. lwz r0, 0(r7)
  424. stw r0, 0(r9)
  425. addi r7, r7, 4
  426. addi r9, r9, 4
  427. cmplw 0, r7, r8
  428. bne 1b
  429. /*
  430. * relocate `hdlr' and `int_return' entries
  431. */
  432. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  433. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  434. 2:
  435. bl trap_reloc
  436. addi r7, r7, 0x100 /* next exception vector */
  437. cmplw 0, r7, r8
  438. blt 2b
  439. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  440. bl trap_reloc
  441. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  442. bl trap_reloc
  443. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  444. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  445. 3:
  446. bl trap_reloc
  447. addi r7, r7, 0x100 /* next exception vector */
  448. cmplw 0, r7, r8
  449. blt 3b
  450. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  451. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  452. 4:
  453. bl trap_reloc
  454. addi r7, r7, 0x100 /* next exception vector */
  455. cmplw 0, r7, r8
  456. blt 4b
  457. mtlr r4 /* restore link register */
  458. blr
  459. #if defined(CONFIG_PATI)
  460. /* Program the PLL */
  461. pll_prog_code_start:
  462. lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
  463. ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
  464. lis r3, (0x55ccaa33)@h
  465. ori r3, r3, (0x55ccaa33)@l
  466. stw r3, 0(r4)
  467. lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
  468. ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
  469. lis r3, CONFIG_SYS_PLPRCR@h
  470. ori r3, r3, CONFIG_SYS_PLPRCR@l
  471. stw r3, 0(r4)
  472. addis r3,0,0x0
  473. ori r3,r3,0xA000
  474. mtctr r3
  475. ..spinlp:
  476. bdnz ..spinlp /* spin loop */
  477. blr
  478. pll_prog_code_end:
  479. nop
  480. blr
  481. #endif