shannon.c 2.6 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Alex Zuepke <azu@sysgo.de>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. /* ------------------------------------------------------------------------- */
  26. /*
  27. * Miscelaneous platform dependent initialisations
  28. */
  29. int board_init (void)
  30. {
  31. DECLARE_GLOBAL_DATA_PTR;
  32. /* memory and cpu-speed are setup before relocation */
  33. /* but if we use InfernoLoader, we must do some inits here */
  34. #ifdef CONFIG_INFERNO
  35. {
  36. unsigned long temp;
  37. __asm__ __volatile__(/* disable MMU, enable icache */
  38. "mrc p15, 0, %0, c1, c0\n"
  39. "bic %0, %0, #0x00002000\n"
  40. "bic %0, %0, #0x0000000f\n"
  41. "orr %0, %0, #0x00001000\n"
  42. "orr %0, %0, #0x00000002\n"
  43. "mcr p15, 0, %0, c1, c0\n"
  44. /* flush caches */
  45. "mov %0, #0\n"
  46. "mcr p15, 0, %0, c7, c7, 0\n"
  47. "mcr p15, 0, %0, c8, c7, 0\n"
  48. : "=r" (temp)
  49. :
  50. : "memory");
  51. /* setup PCMCIA timing */
  52. temp = 0xa0000018;
  53. *(unsigned long *)temp = 0x00060006;
  54. }
  55. #endif /* CONFIG_INFERNO */
  56. /* arch number for shannon */
  57. gd->bd->bi_arch_number = 97;
  58. /* adress of boot parameters */
  59. gd->bd->bi_boot_params = 0xc0000100;
  60. return 0;
  61. }
  62. int dram_init (void)
  63. {
  64. #if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \
  65. defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4)
  66. DECLARE_GLOBAL_DATA_PTR;
  67. bd_t *bd = gd->bd;
  68. #endif
  69. #ifdef PHYS_SDRAM_1
  70. bd->bi_dram[0].start = PHYS_SDRAM_1;
  71. bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  72. #endif
  73. #ifdef PHYS_SDRAM_2
  74. bd->bi_dram[1].start = PHYS_SDRAM_2;
  75. bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  76. #endif
  77. #ifdef PHYS_SDRAM_3
  78. bd->bi_dram[2].start = PHYS_SDRAM_3;
  79. bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  80. #endif
  81. #ifdef PHYS_SDRAM_4
  82. bd->bi_dram[3].start = PHYS_SDRAM_4;
  83. bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
  84. #endif
  85. return (0);
  86. }