ddr.c 2.0 KB

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  1. /*
  2. * Copyright 2008 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <asm/fsl_ddr_sdram.h>
  11. #include <asm/fsl_ddr_dimm_params.h>
  12. static void
  13. get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
  14. {
  15. i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
  16. /* We use soldered memory, but use an SPD EEPROM to describe it.
  17. * The SPD has an unspecified dimm type, but the DDR2 initialization
  18. * code requires a specific type to be specified. This sets the type
  19. * as a standard unregistered SO-DIMM. */
  20. if (spd->dimm_type == 0) {
  21. spd->dimm_type = 0x4;
  22. ((uchar *)spd)[63] += 0x4;
  23. }
  24. }
  25. void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
  26. unsigned int ctrl_num)
  27. {
  28. unsigned int i;
  29. if (ctrl_num) {
  30. printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
  31. return;
  32. }
  33. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
  34. get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
  35. }
  36. void fsl_ddr_board_options(memctl_options_t *popts,
  37. dimm_params_t *pdimm,
  38. unsigned int ctrl_num)
  39. {
  40. /*
  41. * Factors to consider for clock adjust:
  42. * - number of chips on bus
  43. * - position of slot
  44. * - DDR1 vs. DDR2?
  45. * - ???
  46. *
  47. * This needs to be determined on a board-by-board basis.
  48. * 0110 3/4 cycle late
  49. * 0111 7/8 cycle late
  50. */
  51. popts->clk_adjust = 7;
  52. /*
  53. * Factors to consider for CPO:
  54. * - frequency
  55. * - ddr1 vs. ddr2
  56. */
  57. popts->cpo_override = 9;
  58. /*
  59. * Factors to consider for write data delay:
  60. * - number of DIMMs
  61. *
  62. * 1 = 1/4 clock delay
  63. * 2 = 1/2 clock delay
  64. * 3 = 3/4 clock delay
  65. * 4 = 1 clock delay
  66. * 5 = 5/4 clock delay
  67. * 6 = 3/2 clock delay
  68. */
  69. popts->write_data_delay = 3;
  70. /*
  71. * Factors to consider for half-strength driver enable:
  72. * - number of DIMMs installed
  73. */
  74. popts->half_strength_driver_enable = 0;
  75. }