ehci-hcd.c 22 KB

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  1. /*-
  2. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  3. * Copyright (c) 2008, Excito Elektronik i Skåne AB
  4. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2 of
  11. * the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/byteorder.h>
  25. #include <usb.h>
  26. #include <asm/io.h>
  27. #include <malloc.h>
  28. #include <watchdog.h>
  29. #include "ehci.h"
  30. int rootdev;
  31. struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  32. volatile struct ehci_hcor *hcor;
  33. static uint16_t portreset;
  34. static struct QH qh_list __attribute__((aligned(32)));
  35. static struct descriptor {
  36. struct usb_hub_descriptor hub;
  37. struct usb_device_descriptor device;
  38. struct usb_linux_config_descriptor config;
  39. struct usb_linux_interface_descriptor interface;
  40. struct usb_endpoint_descriptor endpoint;
  41. } __attribute__ ((packed)) descriptor = {
  42. {
  43. 0x8, /* bDescLength */
  44. 0x29, /* bDescriptorType: hub descriptor */
  45. 2, /* bNrPorts -- runtime modified */
  46. 0, /* wHubCharacteristics */
  47. 10, /* bPwrOn2PwrGood */
  48. 0, /* bHubCntrCurrent */
  49. {}, /* Device removable */
  50. {} /* at most 7 ports! XXX */
  51. },
  52. {
  53. 0x12, /* bLength */
  54. 1, /* bDescriptorType: UDESC_DEVICE */
  55. cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  56. 9, /* bDeviceClass: UDCLASS_HUB */
  57. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  58. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  59. 64, /* bMaxPacketSize: 64 bytes */
  60. 0x0000, /* idVendor */
  61. 0x0000, /* idProduct */
  62. cpu_to_le16(0x0100), /* bcdDevice */
  63. 1, /* iManufacturer */
  64. 2, /* iProduct */
  65. 0, /* iSerialNumber */
  66. 1 /* bNumConfigurations: 1 */
  67. },
  68. {
  69. 0x9,
  70. 2, /* bDescriptorType: UDESC_CONFIG */
  71. cpu_to_le16(0x19),
  72. 1, /* bNumInterface */
  73. 1, /* bConfigurationValue */
  74. 0, /* iConfiguration */
  75. 0x40, /* bmAttributes: UC_SELF_POWER */
  76. 0 /* bMaxPower */
  77. },
  78. {
  79. 0x9, /* bLength */
  80. 4, /* bDescriptorType: UDESC_INTERFACE */
  81. 0, /* bInterfaceNumber */
  82. 0, /* bAlternateSetting */
  83. 1, /* bNumEndpoints */
  84. 9, /* bInterfaceClass: UICLASS_HUB */
  85. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  86. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  87. 0 /* iInterface */
  88. },
  89. {
  90. 0x7, /* bLength */
  91. 5, /* bDescriptorType: UDESC_ENDPOINT */
  92. 0x81, /* bEndpointAddress:
  93. * UE_DIR_IN | EHCI_INTR_ENDPT
  94. */
  95. 3, /* bmAttributes: UE_INTERRUPT */
  96. 8, /* wMaxPacketSize */
  97. 255 /* bInterval */
  98. },
  99. };
  100. #if defined(CONFIG_EHCI_IS_TDI)
  101. #define ehci_is_TDI() (1)
  102. #else
  103. #define ehci_is_TDI() (0)
  104. #endif
  105. #if defined(CONFIG_EHCI_DCACHE)
  106. /*
  107. * Routines to handle (flush/invalidate) the dcache for the QH and qTD
  108. * structures and data buffers. This is needed on platforms using this
  109. * EHCI support with dcache enabled.
  110. */
  111. static void flush_invalidate(u32 addr, int size, int flush)
  112. {
  113. if (flush)
  114. flush_dcache_range(addr, addr + size);
  115. else
  116. invalidate_dcache_range(addr, addr + size);
  117. }
  118. static void cache_qtd(struct qTD *qtd, int flush)
  119. {
  120. u32 *ptr = (u32 *)qtd->qt_buffer[0];
  121. int len = (qtd->qt_token & 0x7fff0000) >> 16;
  122. flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
  123. if (ptr && len)
  124. flush_invalidate((u32)ptr, len, flush);
  125. }
  126. static inline struct QH *qh_addr(struct QH *qh)
  127. {
  128. return (struct QH *)((u32)qh & 0xffffffe0);
  129. }
  130. static void cache_qh(struct QH *qh, int flush)
  131. {
  132. struct qTD *qtd;
  133. struct qTD *next;
  134. static struct qTD *first_qtd;
  135. /*
  136. * Walk the QH list and flush/invalidate all entries
  137. */
  138. while (1) {
  139. flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
  140. if ((u32)qh & QH_LINK_TYPE_QH)
  141. break;
  142. qh = qh_addr(qh);
  143. qh = (struct QH *)qh->qh_link;
  144. }
  145. qh = qh_addr(qh);
  146. /*
  147. * Save first qTD pointer, needed for invalidating pass on this QH
  148. */
  149. if (flush)
  150. first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
  151. 0xffffffe0);
  152. else
  153. qtd = first_qtd;
  154. /*
  155. * Walk the qTD list and flush/invalidate all entries
  156. */
  157. while (1) {
  158. if (qtd == NULL)
  159. break;
  160. cache_qtd(qtd, flush);
  161. next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
  162. if (next == qtd)
  163. break;
  164. qtd = next;
  165. }
  166. }
  167. static inline void ehci_flush_dcache(struct QH *qh)
  168. {
  169. cache_qh(qh, 1);
  170. }
  171. static inline void ehci_invalidate_dcache(struct QH *qh)
  172. {
  173. cache_qh(qh, 0);
  174. }
  175. #else /* CONFIG_EHCI_DCACHE */
  176. /*
  177. *
  178. */
  179. static inline void ehci_flush_dcache(struct QH *qh)
  180. {
  181. }
  182. static inline void ehci_invalidate_dcache(struct QH *qh)
  183. {
  184. }
  185. #endif /* CONFIG_EHCI_DCACHE */
  186. void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
  187. {
  188. mdelay(50);
  189. }
  190. void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
  191. __attribute__((weak, alias("__ehci_powerup_fixup")));
  192. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
  193. {
  194. uint32_t result;
  195. do {
  196. result = ehci_readl(ptr);
  197. udelay(5);
  198. if (result == ~(uint32_t)0)
  199. return -1;
  200. result &= mask;
  201. if (result == done)
  202. return 0;
  203. usec--;
  204. } while (usec > 0);
  205. return -1;
  206. }
  207. static void ehci_free(void *p, size_t sz)
  208. {
  209. }
  210. static int ehci_reset(void)
  211. {
  212. uint32_t cmd;
  213. uint32_t tmp;
  214. uint32_t *reg_ptr;
  215. int ret = 0;
  216. cmd = ehci_readl(&hcor->or_usbcmd);
  217. cmd = (cmd & ~CMD_RUN) | CMD_RESET;
  218. ehci_writel(&hcor->or_usbcmd, cmd);
  219. ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
  220. if (ret < 0) {
  221. printf("EHCI fail to reset\n");
  222. goto out;
  223. }
  224. if (ehci_is_TDI()) {
  225. reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
  226. tmp = ehci_readl(reg_ptr);
  227. tmp |= USBMODE_CM_HC;
  228. #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
  229. tmp |= USBMODE_BE;
  230. #endif
  231. ehci_writel(reg_ptr, tmp);
  232. }
  233. out:
  234. return ret;
  235. }
  236. static void *ehci_alloc(size_t sz, size_t align)
  237. {
  238. static struct QH qh __attribute__((aligned(32)));
  239. static struct qTD td[3] __attribute__((aligned (32)));
  240. static int ntds;
  241. void *p;
  242. switch (sz) {
  243. case sizeof(struct QH):
  244. p = &qh;
  245. ntds = 0;
  246. break;
  247. case sizeof(struct qTD):
  248. if (ntds == 3) {
  249. debug("out of TDs\n");
  250. return NULL;
  251. }
  252. p = &td[ntds];
  253. ntds++;
  254. break;
  255. default:
  256. debug("unknown allocation size\n");
  257. return NULL;
  258. }
  259. memset(p, 0, sz);
  260. return p;
  261. }
  262. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  263. {
  264. uint32_t addr, delta, next;
  265. int idx;
  266. addr = (uint32_t) buf;
  267. idx = 0;
  268. while (idx < 5) {
  269. td->qt_buffer[idx] = cpu_to_hc32(addr);
  270. td->qt_buffer_hi[idx] = 0;
  271. next = (addr + 4096) & ~4095;
  272. delta = next - addr;
  273. if (delta >= sz)
  274. break;
  275. sz -= delta;
  276. addr = next;
  277. idx++;
  278. }
  279. if (idx == 5) {
  280. debug("out of buffer pointers (%u bytes left)\n", sz);
  281. return -1;
  282. }
  283. return 0;
  284. }
  285. static int
  286. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  287. int length, struct devrequest *req)
  288. {
  289. struct QH *qh;
  290. struct qTD *td;
  291. volatile struct qTD *vtd;
  292. unsigned long ts;
  293. uint32_t *tdp;
  294. uint32_t endpt, token, usbsts;
  295. uint32_t c, toggle;
  296. uint32_t cmd;
  297. int timeout;
  298. int ret = 0;
  299. debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  300. buffer, length, req);
  301. if (req != NULL)
  302. debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  303. req->request, req->request,
  304. req->requesttype, req->requesttype,
  305. le16_to_cpu(req->value), le16_to_cpu(req->value),
  306. le16_to_cpu(req->index));
  307. qh = ehci_alloc(sizeof(struct QH), 32);
  308. if (qh == NULL) {
  309. debug("unable to allocate QH\n");
  310. return -1;
  311. }
  312. qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  313. c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
  314. usb_pipeendpoint(pipe) == 0) ? 1 : 0;
  315. endpt = (8 << 28) |
  316. (c << 27) |
  317. (usb_maxpacket(dev, pipe) << 16) |
  318. (0 << 15) |
  319. (1 << 14) |
  320. (usb_pipespeed(pipe) << 12) |
  321. (usb_pipeendpoint(pipe) << 8) |
  322. (0 << 7) | (usb_pipedevice(pipe) << 0);
  323. qh->qh_endpt1 = cpu_to_hc32(endpt);
  324. endpt = (1 << 30) |
  325. (dev->portnr << 23) |
  326. (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
  327. qh->qh_endpt2 = cpu_to_hc32(endpt);
  328. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  329. td = NULL;
  330. tdp = &qh->qh_overlay.qt_next;
  331. toggle =
  332. usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  333. if (req != NULL) {
  334. td = ehci_alloc(sizeof(struct qTD), 32);
  335. if (td == NULL) {
  336. debug("unable to allocate SETUP td\n");
  337. goto fail;
  338. }
  339. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  340. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  341. token = (0 << 31) |
  342. (sizeof(*req) << 16) |
  343. (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
  344. td->qt_token = cpu_to_hc32(token);
  345. if (ehci_td_buffer(td, req, sizeof(*req)) != 0) {
  346. debug("unable construct SETUP td\n");
  347. ehci_free(td, sizeof(*td));
  348. goto fail;
  349. }
  350. *tdp = cpu_to_hc32((uint32_t) td);
  351. tdp = &td->qt_next;
  352. toggle = 1;
  353. }
  354. if (length > 0 || req == NULL) {
  355. td = ehci_alloc(sizeof(struct qTD), 32);
  356. if (td == NULL) {
  357. debug("unable to allocate DATA td\n");
  358. goto fail;
  359. }
  360. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  361. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  362. token = (toggle << 31) |
  363. (length << 16) |
  364. ((req == NULL ? 1 : 0) << 15) |
  365. (0 << 12) |
  366. (3 << 10) |
  367. ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
  368. td->qt_token = cpu_to_hc32(token);
  369. if (ehci_td_buffer(td, buffer, length) != 0) {
  370. debug("unable construct DATA td\n");
  371. ehci_free(td, sizeof(*td));
  372. goto fail;
  373. }
  374. *tdp = cpu_to_hc32((uint32_t) td);
  375. tdp = &td->qt_next;
  376. }
  377. if (req != NULL) {
  378. td = ehci_alloc(sizeof(struct qTD), 32);
  379. if (td == NULL) {
  380. debug("unable to allocate ACK td\n");
  381. goto fail;
  382. }
  383. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  384. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  385. token = (toggle << 31) |
  386. (0 << 16) |
  387. (1 << 15) |
  388. (0 << 12) |
  389. (3 << 10) |
  390. ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
  391. td->qt_token = cpu_to_hc32(token);
  392. *tdp = cpu_to_hc32((uint32_t) td);
  393. tdp = &td->qt_next;
  394. }
  395. qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
  396. /* Flush dcache */
  397. ehci_flush_dcache(&qh_list);
  398. usbsts = ehci_readl(&hcor->or_usbsts);
  399. ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
  400. /* Enable async. schedule. */
  401. cmd = ehci_readl(&hcor->or_usbcmd);
  402. cmd |= CMD_ASE;
  403. ehci_writel(&hcor->or_usbcmd, cmd);
  404. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
  405. 100 * 1000);
  406. if (ret < 0) {
  407. printf("EHCI fail timeout STD_ASS set\n");
  408. goto fail;
  409. }
  410. /* Wait for TDs to be processed. */
  411. ts = get_timer(0);
  412. vtd = td;
  413. timeout = USB_TIMEOUT_MS(pipe);
  414. do {
  415. /* Invalidate dcache */
  416. ehci_invalidate_dcache(&qh_list);
  417. token = hc32_to_cpu(vtd->qt_token);
  418. if (!(token & 0x80))
  419. break;
  420. WATCHDOG_RESET();
  421. } while (get_timer(ts) < timeout);
  422. /* Check that the TD processing happened */
  423. if (token & 0x80) {
  424. printf("EHCI timed out on TD - token=%#x\n", token);
  425. }
  426. /* Disable async schedule. */
  427. cmd = ehci_readl(&hcor->or_usbcmd);
  428. cmd &= ~CMD_ASE;
  429. ehci_writel(&hcor->or_usbcmd, cmd);
  430. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
  431. 100 * 1000);
  432. if (ret < 0) {
  433. printf("EHCI fail timeout STD_ASS reset\n");
  434. goto fail;
  435. }
  436. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  437. token = hc32_to_cpu(qh->qh_overlay.qt_token);
  438. if (!(token & 0x80)) {
  439. debug("TOKEN=%#x\n", token);
  440. switch (token & 0xfc) {
  441. case 0:
  442. toggle = token >> 31;
  443. usb_settoggle(dev, usb_pipeendpoint(pipe),
  444. usb_pipeout(pipe), toggle);
  445. dev->status = 0;
  446. break;
  447. case 0x40:
  448. dev->status = USB_ST_STALLED;
  449. break;
  450. case 0xa0:
  451. case 0x20:
  452. dev->status = USB_ST_BUF_ERR;
  453. break;
  454. case 0x50:
  455. case 0x10:
  456. dev->status = USB_ST_BABBLE_DET;
  457. break;
  458. default:
  459. dev->status = USB_ST_CRC_ERR;
  460. if ((token & 0x40) == 0x40)
  461. dev->status |= USB_ST_STALLED;
  462. break;
  463. }
  464. dev->act_len = length - ((token >> 16) & 0x7fff);
  465. } else {
  466. dev->act_len = 0;
  467. debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
  468. dev->devnum, ehci_readl(&hcor->or_usbsts),
  469. ehci_readl(&hcor->or_portsc[0]),
  470. ehci_readl(&hcor->or_portsc[1]));
  471. }
  472. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  473. fail:
  474. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  475. while (td != (void *)QT_NEXT_TERMINATE) {
  476. qh->qh_overlay.qt_next = td->qt_next;
  477. ehci_free(td, sizeof(*td));
  478. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  479. }
  480. ehci_free(qh, sizeof(*qh));
  481. return -1;
  482. }
  483. static inline int min3(int a, int b, int c)
  484. {
  485. if (b < a)
  486. a = b;
  487. if (c < a)
  488. a = c;
  489. return a;
  490. }
  491. int
  492. ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
  493. int length, struct devrequest *req)
  494. {
  495. uint8_t tmpbuf[4];
  496. u16 typeReq;
  497. void *srcptr = NULL;
  498. int len, srclen;
  499. uint32_t reg;
  500. uint32_t *status_reg;
  501. if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
  502. printf("The request port(%d) is not configured\n",
  503. le16_to_cpu(req->index) - 1);
  504. return -1;
  505. }
  506. status_reg = (uint32_t *)&hcor->or_portsc[
  507. le16_to_cpu(req->index) - 1];
  508. srclen = 0;
  509. debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  510. req->request, req->request,
  511. req->requesttype, req->requesttype,
  512. le16_to_cpu(req->value), le16_to_cpu(req->index));
  513. typeReq = req->request | req->requesttype << 8;
  514. switch (typeReq) {
  515. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  516. switch (le16_to_cpu(req->value) >> 8) {
  517. case USB_DT_DEVICE:
  518. debug("USB_DT_DEVICE request\n");
  519. srcptr = &descriptor.device;
  520. srclen = 0x12;
  521. break;
  522. case USB_DT_CONFIG:
  523. debug("USB_DT_CONFIG config\n");
  524. srcptr = &descriptor.config;
  525. srclen = 0x19;
  526. break;
  527. case USB_DT_STRING:
  528. debug("USB_DT_STRING config\n");
  529. switch (le16_to_cpu(req->value) & 0xff) {
  530. case 0: /* Language */
  531. srcptr = "\4\3\1\0";
  532. srclen = 4;
  533. break;
  534. case 1: /* Vendor */
  535. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  536. srclen = 14;
  537. break;
  538. case 2: /* Product */
  539. srcptr = "\52\3E\0H\0C\0I\0 "
  540. "\0H\0o\0s\0t\0 "
  541. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  542. srclen = 42;
  543. break;
  544. default:
  545. debug("unknown value DT_STRING %x\n",
  546. le16_to_cpu(req->value));
  547. goto unknown;
  548. }
  549. break;
  550. default:
  551. debug("unknown value %x\n", le16_to_cpu(req->value));
  552. goto unknown;
  553. }
  554. break;
  555. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  556. switch (le16_to_cpu(req->value) >> 8) {
  557. case USB_DT_HUB:
  558. debug("USB_DT_HUB config\n");
  559. srcptr = &descriptor.hub;
  560. srclen = 0x8;
  561. break;
  562. default:
  563. debug("unknown value %x\n", le16_to_cpu(req->value));
  564. goto unknown;
  565. }
  566. break;
  567. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  568. debug("USB_REQ_SET_ADDRESS\n");
  569. rootdev = le16_to_cpu(req->value);
  570. break;
  571. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  572. debug("USB_REQ_SET_CONFIGURATION\n");
  573. /* Nothing to do */
  574. break;
  575. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  576. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  577. tmpbuf[1] = 0;
  578. srcptr = tmpbuf;
  579. srclen = 2;
  580. break;
  581. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  582. memset(tmpbuf, 0, 4);
  583. reg = ehci_readl(status_reg);
  584. if (reg & EHCI_PS_CS)
  585. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  586. if (reg & EHCI_PS_PE)
  587. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  588. if (reg & EHCI_PS_SUSP)
  589. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  590. if (reg & EHCI_PS_OCA)
  591. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  592. if (reg & EHCI_PS_PR)
  593. tmpbuf[0] |= USB_PORT_STAT_RESET;
  594. if (reg & EHCI_PS_PP)
  595. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  596. if (ehci_is_TDI()) {
  597. switch ((reg >> 26) & 3) {
  598. case 0:
  599. break;
  600. case 1:
  601. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  602. break;
  603. case 2:
  604. default:
  605. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  606. break;
  607. }
  608. } else {
  609. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  610. }
  611. if (reg & EHCI_PS_CSC)
  612. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  613. if (reg & EHCI_PS_PEC)
  614. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  615. if (reg & EHCI_PS_OCC)
  616. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  617. if (portreset & (1 << le16_to_cpu(req->index)))
  618. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  619. srcptr = tmpbuf;
  620. srclen = 4;
  621. break;
  622. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  623. reg = ehci_readl(status_reg);
  624. reg &= ~EHCI_PS_CLEAR;
  625. switch (le16_to_cpu(req->value)) {
  626. case USB_PORT_FEAT_ENABLE:
  627. reg |= EHCI_PS_PE;
  628. ehci_writel(status_reg, reg);
  629. break;
  630. case USB_PORT_FEAT_POWER:
  631. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
  632. reg |= EHCI_PS_PP;
  633. ehci_writel(status_reg, reg);
  634. }
  635. break;
  636. case USB_PORT_FEAT_RESET:
  637. if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
  638. !ehci_is_TDI() &&
  639. EHCI_PS_IS_LOWSPEED(reg)) {
  640. /* Low speed device, give up ownership. */
  641. debug("port %d low speed --> companion\n",
  642. req->index - 1);
  643. reg |= EHCI_PS_PO;
  644. ehci_writel(status_reg, reg);
  645. break;
  646. } else {
  647. int ret;
  648. reg |= EHCI_PS_PR;
  649. reg &= ~EHCI_PS_PE;
  650. ehci_writel(status_reg, reg);
  651. /*
  652. * caller must wait, then call GetPortStatus
  653. * usb 2.0 specification say 50 ms resets on
  654. * root
  655. */
  656. ehci_powerup_fixup(status_reg, &reg);
  657. ehci_writel(status_reg, reg & ~EHCI_PS_PR);
  658. /*
  659. * A host controller must terminate the reset
  660. * and stabilize the state of the port within
  661. * 2 milliseconds
  662. */
  663. ret = handshake(status_reg, EHCI_PS_PR, 0,
  664. 2 * 1000);
  665. if (!ret)
  666. portreset |=
  667. 1 << le16_to_cpu(req->index);
  668. else
  669. printf("port(%d) reset error\n",
  670. le16_to_cpu(req->index) - 1);
  671. }
  672. break;
  673. default:
  674. debug("unknown feature %x\n", le16_to_cpu(req->value));
  675. goto unknown;
  676. }
  677. /* unblock posted writes */
  678. (void) ehci_readl(&hcor->or_usbcmd);
  679. break;
  680. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  681. reg = ehci_readl(status_reg);
  682. switch (le16_to_cpu(req->value)) {
  683. case USB_PORT_FEAT_ENABLE:
  684. reg &= ~EHCI_PS_PE;
  685. break;
  686. case USB_PORT_FEAT_C_ENABLE:
  687. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
  688. break;
  689. case USB_PORT_FEAT_POWER:
  690. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
  691. reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
  692. case USB_PORT_FEAT_C_CONNECTION:
  693. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
  694. break;
  695. case USB_PORT_FEAT_OVER_CURRENT:
  696. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
  697. break;
  698. case USB_PORT_FEAT_C_RESET:
  699. portreset &= ~(1 << le16_to_cpu(req->index));
  700. break;
  701. default:
  702. debug("unknown feature %x\n", le16_to_cpu(req->value));
  703. goto unknown;
  704. }
  705. ehci_writel(status_reg, reg);
  706. /* unblock posted write */
  707. (void) ehci_readl(&hcor->or_usbcmd);
  708. break;
  709. default:
  710. debug("Unknown request\n");
  711. goto unknown;
  712. }
  713. mdelay(1);
  714. len = min3(srclen, le16_to_cpu(req->length), length);
  715. if (srcptr != NULL && len > 0)
  716. memcpy(buffer, srcptr, len);
  717. else
  718. debug("Len is 0\n");
  719. dev->act_len = len;
  720. dev->status = 0;
  721. return 0;
  722. unknown:
  723. debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  724. req->requesttype, req->request, le16_to_cpu(req->value),
  725. le16_to_cpu(req->index), le16_to_cpu(req->length));
  726. dev->act_len = 0;
  727. dev->status = USB_ST_STALLED;
  728. return -1;
  729. }
  730. int usb_lowlevel_stop(void)
  731. {
  732. return ehci_hcd_stop();
  733. }
  734. int usb_lowlevel_init(void)
  735. {
  736. uint32_t reg;
  737. uint32_t cmd;
  738. if (ehci_hcd_init() != 0)
  739. return -1;
  740. /* EHCI spec section 4.1 */
  741. if (ehci_reset() != 0)
  742. return -1;
  743. #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
  744. if (ehci_hcd_init() != 0)
  745. return -1;
  746. #endif
  747. /* Set head of reclaim list */
  748. memset(&qh_list, 0, sizeof(qh_list));
  749. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  750. qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
  751. qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
  752. qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  753. qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  754. qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
  755. /* Set async. queue head pointer. */
  756. ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
  757. reg = ehci_readl(&hccr->cr_hcsparams);
  758. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  759. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  760. /* Port Indicators */
  761. if (HCS_INDICATOR(reg))
  762. descriptor.hub.wHubCharacteristics |= 0x80;
  763. /* Port Power Control */
  764. if (HCS_PPC(reg))
  765. descriptor.hub.wHubCharacteristics |= 0x01;
  766. /* Start the host controller. */
  767. cmd = ehci_readl(&hcor->or_usbcmd);
  768. /*
  769. * Philips, Intel, and maybe others need CMD_RUN before the
  770. * root hub will detect new devices (why?); NEC doesn't
  771. */
  772. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  773. cmd |= CMD_RUN;
  774. ehci_writel(&hcor->or_usbcmd, cmd);
  775. /* take control over the ports */
  776. cmd = ehci_readl(&hcor->or_configflag);
  777. cmd |= FLAG_CF;
  778. ehci_writel(&hcor->or_configflag, cmd);
  779. /* unblock posted write */
  780. cmd = ehci_readl(&hcor->or_usbcmd);
  781. mdelay(5);
  782. reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
  783. printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
  784. rootdev = 0;
  785. return 0;
  786. }
  787. int
  788. submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  789. int length)
  790. {
  791. if (usb_pipetype(pipe) != PIPE_BULK) {
  792. debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  793. return -1;
  794. }
  795. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  796. }
  797. int
  798. submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  799. int length, struct devrequest *setup)
  800. {
  801. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  802. debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
  803. return -1;
  804. }
  805. if (usb_pipedevice(pipe) == rootdev) {
  806. if (rootdev == 0)
  807. dev->speed = USB_SPEED_HIGH;
  808. return ehci_submit_root(dev, pipe, buffer, length, setup);
  809. }
  810. return ehci_submit_async(dev, pipe, buffer, length, setup);
  811. }
  812. int
  813. submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  814. int length, int interval)
  815. {
  816. debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  817. dev, pipe, buffer, length, interval);
  818. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  819. }