miiphyutil.c 6.1 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * This provides a bit-banged interface to the ethernet MII management
  25. * channel.
  26. */
  27. #include <common.h>
  28. #include <miiphy.h>
  29. #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  30. /*****************************************************************************
  31. *
  32. * Read the OUI, manufacture's model number, and revision number.
  33. *
  34. * OUI: 22 bits (unsigned int)
  35. * Model: 6 bits (unsigned char)
  36. * Revision: 4 bits (unsigned char)
  37. *
  38. * Returns:
  39. * 0 on success
  40. */
  41. int miiphy_info (unsigned char addr,
  42. unsigned int *oui,
  43. unsigned char *model, unsigned char *rev)
  44. {
  45. unsigned int reg = 0;
  46. unsigned short tmp;
  47. if (miiphy_read (addr, PHY_PHYIDR2, &tmp) != 0) {
  48. #ifdef DEBUG
  49. puts ("PHY ID register 2 read failed\n");
  50. #endif
  51. return (-1);
  52. }
  53. reg = tmp;
  54. #ifdef DEBUG
  55. printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
  56. #endif
  57. if (reg == 0xFFFF) {
  58. /* No physical device present at this address */
  59. return (-1);
  60. }
  61. if (miiphy_read (addr, PHY_PHYIDR1, &tmp) != 0) {
  62. #ifdef DEBUG
  63. puts ("PHY ID register 1 read failed\n");
  64. #endif
  65. return (-1);
  66. }
  67. reg |= tmp << 16;
  68. #ifdef DEBUG
  69. printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
  70. #endif
  71. *oui = ( reg >> 10);
  72. *model = (unsigned char) ((reg >> 4) & 0x0000003F);
  73. *rev = (unsigned char) ( reg & 0x0000000F);
  74. return (0);
  75. }
  76. /*****************************************************************************
  77. *
  78. * Reset the PHY.
  79. * Returns:
  80. * 0 on success
  81. */
  82. int miiphy_reset (unsigned char addr)
  83. {
  84. unsigned short reg;
  85. int loop_cnt;
  86. if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
  87. #ifdef DEBUG
  88. printf ("PHY status read failed\n");
  89. #endif
  90. return (-1);
  91. }
  92. if (miiphy_write (addr, PHY_BMCR, reg | 0x8000) != 0) {
  93. #ifdef DEBUG
  94. puts ("PHY reset failed\n");
  95. #endif
  96. return (-1);
  97. }
  98. #ifdef CONFIG_PHY_RESET_DELAY
  99. udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
  100. #endif
  101. /*
  102. * Poll the control register for the reset bit to go to 0 (it is
  103. * auto-clearing). This should happen within 0.5 seconds per the
  104. * IEEE spec.
  105. */
  106. loop_cnt = 0;
  107. reg = 0x8000;
  108. while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
  109. if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
  110. # ifdef DEBUG
  111. puts ("PHY status read failed\n");
  112. # endif
  113. return (-1);
  114. }
  115. }
  116. if ((reg & 0x8000) == 0) {
  117. return (0);
  118. } else {
  119. puts ("PHY reset timed out\n");
  120. return (-1);
  121. }
  122. return (0);
  123. }
  124. /*****************************************************************************
  125. *
  126. * Determine the ethernet speed (10/100).
  127. */
  128. int miiphy_speed (unsigned char addr)
  129. {
  130. unsigned short reg;
  131. #if defined(CONFIG_PHY_GIGE)
  132. if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
  133. printf ("PHY 1000BT Status read failed\n");
  134. } else {
  135. if (reg != 0xFFFF) {
  136. if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
  137. return (_1000BASET);
  138. }
  139. }
  140. }
  141. #endif /* CONFIG_PHY_GIGE */
  142. /* Check Basic Management Control Register first. */
  143. if (miiphy_read (addr, PHY_BMCR, &reg)) {
  144. puts ("PHY speed read failed, assuming 10bT\n");
  145. return (_10BASET);
  146. }
  147. /* Check if auto-negotiation is on. */
  148. if ((reg & PHY_BMCR_AUTON) != 0) {
  149. /* Get auto-negotiation results. */
  150. if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
  151. puts ("PHY AN speed read failed, assuming 10bT\n");
  152. return (_10BASET);
  153. }
  154. if ((reg & PHY_ANLPAR_100) != 0) {
  155. return (_100BASET);
  156. } else {
  157. return (_10BASET);
  158. }
  159. }
  160. /* Get speed from basic control settings. */
  161. else if (reg & PHY_BMCR_100MB) {
  162. return (_100BASET);
  163. } else {
  164. return (_10BASET);
  165. }
  166. }
  167. /*****************************************************************************
  168. *
  169. * Determine full/half duplex.
  170. */
  171. int miiphy_duplex (unsigned char addr)
  172. {
  173. unsigned short reg;
  174. #if defined(CONFIG_PHY_GIGE)
  175. if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
  176. printf ("PHY 1000BT Status read failed\n");
  177. } else {
  178. if ( (reg != 0xFFFF) &&
  179. (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
  180. if ((reg & PHY_1000BTSR_1000FD) !=0) {
  181. return (FULL);
  182. } else {
  183. return (HALF);
  184. }
  185. }
  186. }
  187. #endif /* CONFIG_PHY_GIGE */
  188. /* Check Basic Management Control Register first. */
  189. if (miiphy_read (addr, PHY_BMCR, &reg)) {
  190. puts ("PHY duplex read failed, assuming half duplex\n");
  191. return (HALF);
  192. }
  193. /* Check if auto-negotiation is on. */
  194. if ((reg & PHY_BMCR_AUTON) != 0) {
  195. /* Get auto-negotiation results. */
  196. if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
  197. puts ("PHY AN duplex read failed, assuming half duplex\n");
  198. return (HALF);
  199. }
  200. if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
  201. return (FULL);
  202. } else {
  203. return (HALF);
  204. }
  205. }
  206. /* Get speed from basic control settings. */
  207. else if (reg & PHY_BMCR_DPLX) {
  208. return (FULL);
  209. } else {
  210. return (HALF);
  211. }
  212. }
  213. #ifdef CFG_FAULT_ECHO_LINK_DOWN
  214. /*****************************************************************************
  215. *
  216. * Determine link status
  217. */
  218. int miiphy_link (unsigned char addr)
  219. {
  220. unsigned short reg;
  221. /* dummy read; needed to latch some phys */
  222. (void)miiphy_read(addr, PHY_BMSR, &reg);
  223. if (miiphy_read (addr, PHY_BMSR, &reg)) {
  224. puts ("PHY_BMSR read failed, assuming no link\n");
  225. return (0);
  226. }
  227. /* Determine if a link is active */
  228. if ((reg & PHY_BMSR_LS) != 0) {
  229. return (1);
  230. } else {
  231. return (0);
  232. }
  233. }
  234. #endif
  235. #endif /* CONFIG_MII || (CONFIG_COMMANDS & CFG_CMD_MII) */