delta.h 6.1 KB

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  1. /*
  2. * Configuation settings for the Delta board.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef __CONFIG_H
  23. #define __CONFIG_H
  24. /*
  25. * High Level Configuration Options
  26. * (easy to change)
  27. */
  28. #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
  29. #define CONFIG_DELTA 1 /* Delta board */
  30. /* #define CONFIG_LCD 1 */
  31. #ifdef CONFIG_LCD
  32. #define CONFIG_SHARP_LM8V31
  33. #endif
  34. /* #define CONFIG_MMC 1 */
  35. #define BOARD_LATE_INIT 1
  36. #undef CONFIG_SKIP_RELOCATE_UBOOT
  37. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  38. /*
  39. * Size of malloc() pool
  40. */
  41. #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
  42. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  43. /*
  44. * Hardware drivers
  45. */
  46. #undef TURN_ON_ETHERNET
  47. #ifdef TURN_ON_ETHERNET
  48. # define CONFIG_DRIVER_SMC91111 1
  49. # define CONFIG_SMC91111_BASE 0x14000300
  50. # define CONFIG_SMC91111_EXT_PHY
  51. # define CONFIG_SMC_USE_32_BIT
  52. # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
  53. #endif
  54. /*
  55. * select serial console configuration
  56. */
  57. #define CONFIG_FFUART 1
  58. /* allow to overwrite serial and ethaddr */
  59. #define CONFIG_ENV_OVERWRITE
  60. #define CONFIG_BAUDRATE 115200
  61. /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
  62. #ifdef TURN_ON_ETHERNET
  63. # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
  64. #else
  65. # define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \
  66. & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS))
  67. #endif
  68. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  69. #include <cmd_confdefs.h>
  70. #define CONFIG_BOOTDELAY -1
  71. #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
  72. #define CONFIG_NETMASK 255.255.0.0
  73. #define CONFIG_IPADDR 192.168.0.21
  74. #define CONFIG_SERVERIP 192.168.0.250
  75. #define CONFIG_BOOTCOMMAND "bootm 80000"
  76. #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
  77. #define CONFIG_CMDLINE_TAG
  78. #define CONFIG_TIMESTAMP
  79. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  80. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  81. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  82. #endif
  83. /*
  84. * Miscellaneous configurable options
  85. */
  86. #define CFG_HUSH_PARSER 1
  87. #define CFG_PROMPT_HUSH_PS2 "> "
  88. #define CFG_LONGHELP /* undef to save memory */
  89. #ifdef CFG_HUSH_PARSER
  90. #define CFG_PROMPT "$ " /* Monitor Command Prompt */
  91. #else
  92. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  93. #endif
  94. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  95. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  96. #define CFG_MAXARGS 16 /* max number of command args */
  97. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  98. #define CFG_DEVICE_NULLDEV 1
  99. #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
  100. #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
  101. #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  102. #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
  103. #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
  104. #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
  105. /* valid baudrates */
  106. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  107. /* #define CFG_MMC_BASE 0xF0000000 */
  108. /*
  109. * Stack sizes
  110. *
  111. * The stack sizes are set up in start.S using the settings below
  112. */
  113. #define CONFIG_STACKSIZE (128*1024) /* regular stack */
  114. #ifdef CONFIG_USE_IRQ
  115. #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  116. #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  117. #endif
  118. /*
  119. * Physical Memory Map
  120. */
  121. #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
  122. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  123. #define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
  124. #define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
  125. #define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
  126. #define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
  127. #define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
  128. #define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
  129. #define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
  130. #define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
  131. #define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
  132. #undef CFG_SKIP_DRAM_SCRUB
  133. /*
  134. * NAND Flash
  135. */
  136. /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
  137. #define CONFIG_NEW_NAND_CODE
  138. #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
  139. #undef CFG_NAND1_BASE
  140. #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
  141. #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  142. /* nand timeout values */
  143. #define CFG_NAND_PROG_ERASE_TO 3000
  144. #define CFG_NAND_OTHER_TO 100
  145. #define CFG_NAND_SENDCMD_RETRY 3
  146. #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
  147. /* NAND Timing Parameters (in ns) */
  148. #define NAND_TIMING_tCH 10
  149. #define NAND_TIMING_tCS 0
  150. #define NAND_TIMING_tWH 20
  151. #define NAND_TIMING_tWP 40
  152. #define NAND_TIMING_tRH 20
  153. #define NAND_TIMING_tRP 40
  154. #define NAND_TIMING_tR 11123
  155. #define NAND_TIMING_tWHR 100
  156. #define NAND_TIMING_tAR 10
  157. /* NAND debugging */
  158. #define CFG_DFC_DEBUG1 /* usefull */
  159. #undef CFG_DFC_DEBUG2 /* noisy */
  160. #undef CFG_DFC_DEBUG3 /* extremly noisy */
  161. #define CONFIG_MTD_DEBUG
  162. #define CONFIG_MTD_DEBUG_VERBOSE 1
  163. #define ADDR_COLUMN 1
  164. #define ADDR_PAGE 2
  165. #define ADDR_COLUMN_PAGE 3
  166. #define NAND_ChipID_UNKNOWN 0x00
  167. #define NAND_MAX_FLOORS 1
  168. #define NAND_MAX_CHIPS 1
  169. #define CFG_NO_FLASH 1
  170. #define CFG_ENV_IS_IN_NAND 1
  171. #define CFG_ENV_OFFSET 0x40000
  172. #define CFG_ENV_OFFSET_REDUND 0x44000
  173. #define CFG_ENV_SIZE 0x4000
  174. #endif /* __CONFIG_H */