lowlevel_init.S 13 KB

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  1. /*
  2. * Memory Setup stuff - taken from blob memsetup.S
  3. *
  4. * Copyright (C) 2009 Samsung Electronics
  5. * Kyungmin Park <kyungmin.park@samsung.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <config.h>
  26. #include <version.h>
  27. #include <asm/arch/cpu.h>
  28. #include <asm/arch/clock.h>
  29. #include <asm/arch/power.h>
  30. /*
  31. * Register usages:
  32. *
  33. * r5 has zero always
  34. * r7 has S5PC100 GPIO base, 0xE0300000
  35. * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
  36. * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
  37. */
  38. _TEXT_BASE:
  39. .word TEXT_BASE
  40. .globl lowlevel_init
  41. lowlevel_init:
  42. mov r11, lr
  43. /* r5 has always zero */
  44. mov r5, #0
  45. ldr r7, =S5PC100_GPIO_BASE
  46. ldr r8, =S5PC100_GPIO_BASE
  47. /* Read CPU ID */
  48. ldr r2, =S5PC1XX_PRO_ID
  49. ldr r0, [r2]
  50. mov r1, #0x00010000
  51. and r0, r0, r1
  52. cmp r0, r5
  53. beq 100f
  54. ldr r8, =S5PC110_GPIO_BASE
  55. 100:
  56. /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
  57. cmp r7, r8
  58. beq skip_check_didle @ Support C110 only
  59. ldr r0, =S5PC110_RST_STAT
  60. ldr r1, [r0]
  61. and r1, r1, #0x000D0000
  62. cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
  63. beq didle_wakeup
  64. cmp r7, r8
  65. skip_check_didle:
  66. addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
  67. addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
  68. ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
  69. bic r1, r1, #(0xf << 4) @ 1 * 4-bit
  70. orr r1, r1, #(0x1 << 4)
  71. str r1, [r0, #0x0] @ GPIO_CON_OFFSET
  72. ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
  73. #ifdef CONFIG_ONENAND_IPL
  74. orr r1, r1, #(1 << 1) @ 1 * 1-bit
  75. #else
  76. bic r1, r1, #(1 << 1)
  77. #endif
  78. str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
  79. /* Don't setup at s5pc100 */
  80. beq 100f
  81. /*
  82. * Initialize Async Register Setting for EVT1
  83. * Because we are setting EVT1 as the default value of EVT0,
  84. * setting EVT0 as well does not make things worse.
  85. * Thus, for the simplicity, we set for EVT0, too
  86. *
  87. * The "Async Registers" are:
  88. * 0xE0F0_0000
  89. * 0xE1F0_0000
  90. * 0xF180_0000
  91. * 0xF190_0000
  92. * 0xF1A0_0000
  93. * 0xF1B0_0000
  94. * 0xF1C0_0000
  95. * 0xF1D0_0000
  96. * 0xF1E0_0000
  97. * 0xF1F0_0000
  98. * 0xFAF0_0000
  99. */
  100. ldr r0, =0xe0f00000
  101. ldr r1, [r0]
  102. bic r1, r1, #0x1
  103. str r1, [r0]
  104. ldr r0, =0xe1f00000
  105. ldr r1, [r0]
  106. bic r1, r1, #0x1
  107. str r1, [r0]
  108. ldr r0, =0xf1800000
  109. ldr r1, [r0]
  110. bic r1, r1, #0x1
  111. str r1, [r0]
  112. ldr r0, =0xf1900000
  113. ldr r1, [r0]
  114. bic r1, r1, #0x1
  115. str r1, [r0]
  116. ldr r0, =0xf1a00000
  117. ldr r1, [r0]
  118. bic r1, r1, #0x1
  119. str r1, [r0]
  120. ldr r0, =0xf1b00000
  121. ldr r1, [r0]
  122. bic r1, r1, #0x1
  123. str r1, [r0]
  124. ldr r0, =0xf1c00000
  125. ldr r1, [r0]
  126. bic r1, r1, #0x1
  127. str r1, [r0]
  128. ldr r0, =0xf1d00000
  129. ldr r1, [r0]
  130. bic r1, r1, #0x1
  131. str r1, [r0]
  132. ldr r0, =0xf1e00000
  133. ldr r1, [r0]
  134. bic r1, r1, #0x1
  135. str r1, [r0]
  136. ldr r0, =0xf1f00000
  137. ldr r1, [r0]
  138. bic r1, r1, #0x1
  139. str r1, [r0]
  140. ldr r0, =0xfaf00000
  141. ldr r1, [r0]
  142. bic r1, r1, #0x1
  143. str r1, [r0]
  144. /*
  145. * Diable ABB block to reduce sleep current at low temperature
  146. * Note that it's hidden register setup don't modify it
  147. */
  148. ldr r0, =0xE010C300
  149. ldr r1, =0x00800000
  150. str r1, [r0]
  151. 100:
  152. /* IO retension release */
  153. ldreq r0, =S5PC100_OTHERS @ 0xE0108200
  154. ldrne r0, =S5PC110_OTHERS @ 0xE010E000
  155. ldr r1, [r0]
  156. ldreq r2, =(1 << 31) @ IO_RET_REL
  157. ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
  158. orr r1, r1, r2
  159. /* Do not release retention here for S5PC110 */
  160. streq r1, [r0]
  161. #ifndef CONFIG_ONENAND_IPL
  162. /* Disable Watchdog */
  163. ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
  164. ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
  165. str r5, [r0]
  166. /* setting SRAM */
  167. ldreq r0, =S5PC100_SROMC_BASE
  168. ldrne r0, =S5PC110_SROMC_BASE
  169. ldr r1, =0x9
  170. str r1, [r0]
  171. #endif
  172. /* S5PC100 has 3 groups of interrupt sources */
  173. ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
  174. ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
  175. add r1, r0, #0x00100000
  176. add r2, r0, #0x00200000
  177. /* Disable all interrupts (VIC0, VIC1 and VIC2) */
  178. mvn r3, #0x0
  179. str r3, [r0, #0x14] @ INTENCLEAR
  180. str r3, [r1, #0x14] @ INTENCLEAR
  181. str r3, [r2, #0x14] @ INTENCLEAR
  182. #ifndef CONFIG_ONENAND_IPL
  183. /* Set all interrupts as IRQ */
  184. str r5, [r0, #0xc] @ INTSELECT
  185. str r5, [r1, #0xc] @ INTSELECT
  186. str r5, [r2, #0xc] @ INTSELECT
  187. /* Pending Interrupt Clear */
  188. str r5, [r0, #0xf00] @ INTADDRESS
  189. str r5, [r1, #0xf00] @ INTADDRESS
  190. str r5, [r2, #0xf00] @ INTADDRESS
  191. #endif
  192. #ifndef CONFIG_ONENAND_IPL
  193. /* for UART */
  194. bl uart_asm_init
  195. bl internal_ram_init
  196. #endif
  197. #ifdef CONFIG_ONENAND_IPL
  198. /* init system clock */
  199. bl system_clock_init
  200. /* OneNAND Sync Read Support at S5PC110 only
  201. * RM[15] : Sync Read
  202. * BRWL[14:12] : 7 CLK
  203. * BL[11:9] : Continuous
  204. * VHF[3] : Very High Frequency Enable (Over 83MHz)
  205. * HF[2] : High Frequency Enable (Over 66MHz)
  206. * WM[1] : Sync Write
  207. */
  208. cmp r7, r8
  209. ldrne r1, =0xE006
  210. ldrne r0, =0xB001E442
  211. strneh r1, [r0]
  212. /*
  213. * GCE[26] : Gated Clock Enable
  214. * RPE[17] : Enables Read Prefetch
  215. */
  216. ldrne r1, =((1 << 26) | (1 << 17) | 0xE006)
  217. ldrne r0, =0xB0600000
  218. strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
  219. ldrne r1, =0x1212
  220. strne r1, [r0, #0x108]
  221. /* Board detection to set proper memory configuration */
  222. cmp r7, r8
  223. moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
  224. movne r9, #2 /* r9 has 2Gib default at s5pc110 */
  225. ldr r2, =0xE0200200
  226. ldr r4, [r2, #0x48]
  227. bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */
  228. bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */
  229. bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */
  230. str r1, [r2, #0x48]
  231. /* For write completion */
  232. nop
  233. nop
  234. ldr r3, [r2, #0x44]
  235. and r1, r3, #(0x7 << 2)
  236. mov r1, r1, lsr #2
  237. cmp r1, #0x5
  238. moveq r9, #3
  239. cmp r1, #0x6
  240. moveq r9, #1
  241. cmp r1, #0x7
  242. moveq r9, #2
  243. and r0, r3, #(0x1 << 1)
  244. mov r0, r0, lsr #1
  245. orr r1, r1, r0, lsl #3
  246. cmp r1, #0x8
  247. moveq r9, #3
  248. and r1, r3, #(0x7 << 2)
  249. mov r1, r1, lsr #2
  250. and r0, r3, #(0x1 << 7)
  251. mov r0, r0, lsr #7
  252. orr r1, r1, r0, lsl #3
  253. cmp r1, #0x9
  254. moveq r9, #3
  255. str r4, [r2, #0x48] /* Restore PULLUP configuration */
  256. bl mem_ctrl_asm_init
  257. /* Wakeup support. Don't know if it's going to be used, untested. */
  258. ldreq r0, =S5PC100_RST_STAT
  259. ldrne r0, =S5PC110_RST_STAT
  260. ldr r1, [r0]
  261. biceq r1, r1, #0xfffffff7
  262. moveq r2, #(1 << 3)
  263. bicne r1, r1, #0xfffeffff
  264. movne r2, #(1 << 16)
  265. cmp r1, r2
  266. bne 1f
  267. wakeup:
  268. /* turn off L2 cache */
  269. bl l2_cache_disable
  270. cmp r7, r8
  271. ldreq r0, =0xC100
  272. ldrne r0, =0xC110
  273. /* invalidate L2 cache also */
  274. bl invalidate_dcache
  275. /* turn on L2 cache */
  276. bl l2_cache_enable
  277. cmp r7, r8
  278. /* Load return address and jump to kernel */
  279. ldreq r0, =S5PC100_INFORM0
  280. ldrne r0, =S5PC110_INFORM0
  281. /* r1 = physical address of s5pc1xx_cpu_resume function */
  282. ldr r1, [r0]
  283. /* Jump to kernel (sleep-s5pc1xx.S) */
  284. mov pc, r1
  285. nop
  286. nop
  287. #else
  288. cmp r7, r8
  289. /* Clear wakeup status register */
  290. ldreq r0, =S5PC100_WAKEUP_STAT
  291. ldrne r0, =S5PC110_WAKEUP_STAT
  292. ldr r1, [r0]
  293. str r1, [r0]
  294. /* IO retension release */
  295. ldreq r0, =S5PC100_OTHERS @ 0xE0108200
  296. ldrne r0, =S5PC110_OTHERS @ 0xE010E000
  297. ldr r1, [r0]
  298. ldreq r2, =(1 << 31) @ IO_RET_REL
  299. ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
  300. orr r1, r1, r2
  301. str r1, [r0]
  302. #endif
  303. b 1f
  304. didle_wakeup:
  305. /* Wait when APLL is locked */
  306. ldr r0, =0xE0100100 @ S5PC110_APLL_CON
  307. lockloop:
  308. ldr r1, [r0]
  309. and r1, r1, #(1 << 29)
  310. cmp r1, #(1 << 29)
  311. bne lockloop
  312. ldr r0, =S5PC110_INFORM0
  313. ldr r1, [r0]
  314. mov pc, r1
  315. nop
  316. nop
  317. nop
  318. nop
  319. nop
  320. 1:
  321. mov lr, r11
  322. mov pc, lr
  323. /*
  324. * system_clock_init: Initialize core clock and bus clock.
  325. * void system_clock_init(void)
  326. */
  327. system_clock_init:
  328. ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
  329. /* Check S5PC100 */
  330. cmp r7, r8
  331. bne 110f
  332. 100:
  333. /* Set Lock Time */
  334. ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
  335. str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
  336. str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
  337. str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
  338. str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
  339. /* S5P_APLL_CON */
  340. ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
  341. str r1, [r0, #0x100]
  342. /* S5P_MPLL_CON */
  343. ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
  344. str r1, [r0, #0x104]
  345. /* S5P_EPLL_CON */
  346. ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
  347. str r1, [r0, #0x108]
  348. /* S5P_HPLL_CON */
  349. ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
  350. str r1, [r0, #0x10C]
  351. ldr r1, [r0, #0x300]
  352. ldr r2, =0x00003fff
  353. bic r1, r1, r2
  354. ldr r2, =0x00011301
  355. orr r1, r1, r2
  356. str r1, [r0, #0x300]
  357. ldr r1, [r0, #0x304]
  358. ldr r2, =0x00011110
  359. orr r1, r1, r2
  360. str r1, [r0, #0x304]
  361. ldr r1, =0x00000001
  362. str r1, [r0, #0x308]
  363. /* Set Source Clock */
  364. ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
  365. str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
  366. b 200f
  367. 110:
  368. ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
  369. /* Set OSC_FREQ value */
  370. ldr r1, =0xf
  371. str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
  372. /* Set MTC_STABLE value */
  373. ldr r1, =0xffffffff
  374. str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
  375. /* Set CLAMP_STABLE value */
  376. ldr r1, =0x3ff03ff
  377. str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
  378. ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
  379. /* Set Clock divider */
  380. ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
  381. str r1, [r0, #0x300]
  382. ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
  383. str r1, [r0, #0x310]
  384. /* Set Lock Time */
  385. ldr r1, =0x2cf @ Locktime : 30us
  386. str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
  387. ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
  388. str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
  389. str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
  390. str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
  391. /* S5PC110_APLL_CON */
  392. ldr r1, =0x80C80601 @ 800MHz
  393. str r1, [r0, #0x100]
  394. /* S5PC110_MPLL_CON */
  395. ldr r1, =0x829B0C01 @ 667MHz
  396. str r1, [r0, #0x108]
  397. /* S5PC110_EPLL_CON */
  398. ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
  399. str r1, [r0, #0x110]
  400. /* S5PC110_VPLL_CON */
  401. ldr r1, =0x806C0603 @ 54MHz
  402. str r1, [r0, #0x120]
  403. /* Set Source Clock */
  404. ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
  405. str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
  406. /* OneDRAM(DMC0) clock setting */
  407. ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
  408. str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
  409. ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
  410. str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
  411. /* XCLKOUT = XUSBXTI 24MHz */
  412. add r2, r0, #0xE000 @ S5PC110_OTHERS
  413. ldr r1, [r2]
  414. orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
  415. str r1, [r2]
  416. /* CLK_IP0 */
  417. ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
  418. str r1, [r0, #0x460] @ S5PC110_CLK_IP0
  419. /* CLK_IP1 */
  420. ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
  421. @ NANDXL[24]
  422. str r1, [r0, #0x464] @ S5PC110_CLK_IP1
  423. /* CLK_IP2 */
  424. ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
  425. @ HOSTIF[10] HSMMC0[16]
  426. @ HSMMC2[18] VIC[27:24]
  427. str r1, [r0, #0x468] @ S5PC110_CLK_IP2
  428. /* CLK_IP3 */
  429. ldr r1, =0x8eff038c @ I2C[8:6]
  430. @ SYSTIMER[16] UART0[17]
  431. @ UART1[18] UART2[19]
  432. @ UART3[20] WDT[22]
  433. @ PWM[23] GPIO[26] SYSCON[27]
  434. str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
  435. /* CLK_IP4 */
  436. ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
  437. str r1, [r0, #0x470] @ S5PC110_CLK_IP3
  438. 200:
  439. /* wait at least 200us to stablize all clock */
  440. mov r2, #0x10000
  441. 1: subs r2, r2, #1
  442. bne 1b
  443. mov pc, lr
  444. #ifndef CONFIG_ONENAND_IPL
  445. internal_ram_init:
  446. ldreq r0, =0xE3800000
  447. ldrne r0, =0xF1500000
  448. ldr r1, =0x0
  449. str r1, [r0]
  450. mov pc, lr
  451. #endif
  452. #ifndef CONFIG_ONENAND_IPL
  453. /*
  454. * uart_asm_init: Initialize UART's pins
  455. */
  456. uart_asm_init:
  457. /* set GPIO to enable UART0-UART4 */
  458. mov r0, r8
  459. ldr r1, =0x22222222
  460. str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
  461. ldr r1, =0x00002222
  462. str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
  463. /* Check S5PC100 */
  464. cmp r7, r8
  465. bne 110f
  466. /* UART_SEL GPK0[5] at S5PC100 */
  467. add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
  468. ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
  469. bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
  470. orr r1, r1, #(0x1 << 20) @ Output
  471. str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
  472. ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
  473. bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
  474. orr r1, r1, #(0x2 << 10) @ Pull-up enabled
  475. str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
  476. ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
  477. orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
  478. str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
  479. b 200f
  480. 110:
  481. /*
  482. * Note that the following address
  483. * 0xE020'0360 is reserved address at S5PC100
  484. */
  485. /* UART_SEL MP0_5[7] at S5PC110 */
  486. add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
  487. ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
  488. bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
  489. orr r1, r1, #(0x1 << 28) @ Output
  490. str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
  491. ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
  492. bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
  493. orr r1, r1, #(0x2 << 14) @ Pull-up enabled
  494. str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
  495. ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
  496. orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
  497. str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
  498. 200:
  499. mov pc, lr
  500. #endif