usb_ohci.c 46 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200.
  3. *
  4. * (C) Copyright 2003
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * Note: Much of this code has been derived from Linux 2.4
  8. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  9. * (C) Copyright 2000-2002 David Brownell
  10. *
  11. * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  12. * ebenard@eukrea.com - based on s3c24x0's driver
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. *
  32. */
  33. /*
  34. * IMPORTANT NOTES
  35. * 1 - you MUST define LITTLEENDIAN in the configuration file for the
  36. * board or this driver will NOT work!
  37. * 2 - this driver is intended for use with USB Mass Storage Devices
  38. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  39. * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  40. * to activate workaround for bug #41 or this driver will NOT work!
  41. */
  42. #include <common.h>
  43. /* #include <pci.h> no PCI on the S3C24X0 */
  44. #ifdef CONFIG_USB_OHCI
  45. /* mk: are these really required? */
  46. #if defined(CONFIG_S3C2400)
  47. # include <s3c2400.h>
  48. #elif defined(CONFIG_S3C2410)
  49. # include <s3c2410.h>
  50. #elif defined(CONFIG_ARM920T)
  51. # include <asm/arch/hardware.h>
  52. #elif defined(CONFIG_CPU_MONAHANS)
  53. # include <asm/arch/pxa-regs.h>
  54. #elif defined(CONFIG_MPC5200)
  55. # include <mpc5xxx.h>
  56. #endif
  57. #include <malloc.h>
  58. #include <usb.h>
  59. #include "usb_ohci.h"
  60. #undef S3C24X0_merge
  61. #if defined(CONFIG_ARM920T) || \
  62. defined(CONFIG_S3C2400) || \
  63. defined(CONFIG_S3C2410)
  64. # define OHCI_USE_NPS /* force NoPowerSwitching mode */
  65. #endif
  66. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  67. /* For initializing controller (mask in an HCFS mode too) */
  68. #define OHCI_CONTROL_INIT \
  69. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  70. #define readl(a) (*((vu_long *)(a)))
  71. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  72. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  73. #undef DEBUG
  74. #ifdef DEBUG
  75. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  76. #else
  77. #define dbg(format, arg...) do {} while(0)
  78. #endif /* DEBUG */
  79. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  80. #undef SHOW_INFO
  81. #ifdef SHOW_INFO
  82. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  83. #else
  84. #define info(format, arg...) do {} while(0)
  85. #endif
  86. #define m16_swap(x) swap_16(x)
  87. #define m32_swap(x) swap_32(x)
  88. /* global ohci_t */
  89. static ohci_t gohci;
  90. /* this must be aligned to a 256 byte boundary */
  91. struct ohci_hcca ghcca[1];
  92. /* a pointer to the aligned storage */
  93. struct ohci_hcca *phcca;
  94. /* this allocates EDs for all possible endpoints */
  95. struct ohci_device ohci_dev;
  96. /* urb_priv */
  97. urb_priv_t urb_priv;
  98. /* RHSC flag */
  99. int got_rhsc;
  100. /* device which was disconnected */
  101. struct usb_device *devgone;
  102. #ifdef S3C24X0_merge
  103. /* flag guarding URB transation */
  104. int urb_finished = 0;
  105. #endif
  106. /*-------------------------------------------------------------------------*/
  107. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  108. * The erratum (#4) description is incorrect. AMD's workaround waits
  109. * till some bits (mostly reserved) are clear; ok for all revs.
  110. */
  111. #define OHCI_QUIRK_AMD756 0xabcd
  112. #define read_roothub(hc, register, mask) ({ \
  113. u32 temp = readl (&hc->regs->roothub.register); \
  114. if (hc->flags & OHCI_QUIRK_AMD756) \
  115. while (temp & mask) \
  116. temp = readl (&hc->regs->roothub.register); \
  117. temp; })
  118. static u32 roothub_a (struct ohci *hc)
  119. { return read_roothub (hc, a, 0xfc0fe000); }
  120. static inline u32 roothub_b (struct ohci *hc)
  121. { return readl (&hc->regs->roothub.b); }
  122. static inline u32 roothub_status (struct ohci *hc)
  123. { return readl (&hc->regs->roothub.status); }
  124. static u32 roothub_portstatus (struct ohci *hc, int i)
  125. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  126. /* forward declaration */
  127. static int hc_interrupt (void);
  128. static void
  129. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  130. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  131. /*-------------------------------------------------------------------------*
  132. * URB support functions
  133. *-------------------------------------------------------------------------*/
  134. /* free HCD-private data associated with this URB */
  135. static void urb_free_priv (urb_priv_t * urb)
  136. {
  137. int i;
  138. int last;
  139. struct td * td;
  140. last = urb->length - 1;
  141. if (last >= 0) {
  142. for (i = 0; i <= last; i++) {
  143. td = urb->td[i];
  144. if (td) {
  145. td->usb_dev = NULL;
  146. urb->td[i] = NULL;
  147. }
  148. }
  149. }
  150. }
  151. /*-------------------------------------------------------------------------*/
  152. #ifdef DEBUG
  153. static int sohci_get_current_frame_number (struct usb_device * dev);
  154. /* debug| print the main components of an URB
  155. * small: 0) header + data packets 1) just header */
  156. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  157. int transfer_len, struct devrequest * setup, char * str, int small)
  158. {
  159. urb_priv_t * purb = &urb_priv;
  160. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  161. str,
  162. sohci_get_current_frame_number (dev),
  163. usb_pipedevice (pipe),
  164. usb_pipeendpoint (pipe),
  165. usb_pipeout (pipe)? 'O': 'I',
  166. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  167. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  168. purb->actual_length,
  169. transfer_len, dev->status);
  170. #ifdef OHCI_VERBOSE_DEBUG
  171. if (!small) {
  172. int i, len;
  173. if (usb_pipecontrol (pipe)) {
  174. printf (__FILE__ ": cmd(8):");
  175. for (i = 0; i < 8 ; i++)
  176. printf (" %02x", ((__u8 *) setup) [i]);
  177. printf ("\n");
  178. }
  179. if (transfer_len > 0 && buffer) {
  180. printf (__FILE__ ": data(%d/%d):",
  181. purb->actual_length,
  182. transfer_len);
  183. len = usb_pipeout (pipe)?
  184. transfer_len: purb->actual_length;
  185. for (i = 0; i < 16 && i < len; i++)
  186. printf (" %02x", ((__u8 *) buffer) [i]);
  187. printf ("%s\n", i < len? "...": "");
  188. }
  189. }
  190. #endif
  191. }
  192. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  193. void ep_print_int_eds (ohci_t *ohci, char * str) {
  194. int i, j;
  195. __u32 * ed_p;
  196. for (i= 0; i < 32; i++) {
  197. j = 5;
  198. ed_p = &(ohci->hcca->int_table [i]);
  199. if (*ed_p == 0)
  200. continue;
  201. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  202. while (*ed_p != 0 && j--) {
  203. ed_t *ed = (ed_t *)m32_swap(ed_p);
  204. printf (" ed: %4x;", ed->hwINFO);
  205. ed_p = &ed->hwNextED;
  206. }
  207. printf ("\n");
  208. }
  209. }
  210. static void ohci_dump_intr_mask (char *label, __u32 mask)
  211. {
  212. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  213. label,
  214. mask,
  215. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  216. (mask & OHCI_INTR_OC) ? " OC" : "",
  217. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  218. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  219. (mask & OHCI_INTR_UE) ? " UE" : "",
  220. (mask & OHCI_INTR_RD) ? " RD" : "",
  221. (mask & OHCI_INTR_SF) ? " SF" : "",
  222. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  223. (mask & OHCI_INTR_SO) ? " SO" : ""
  224. );
  225. }
  226. static void maybe_print_eds (char *label, __u32 value)
  227. {
  228. ed_t *edp = (ed_t *)value;
  229. if (value) {
  230. dbg ("%s %08x", label, value);
  231. dbg ("%08x", edp->hwINFO);
  232. dbg ("%08x", edp->hwTailP);
  233. dbg ("%08x", edp->hwHeadP);
  234. dbg ("%08x", edp->hwNextED);
  235. }
  236. }
  237. static char * hcfs2string (int state)
  238. {
  239. switch (state) {
  240. case OHCI_USB_RESET: return "reset";
  241. case OHCI_USB_RESUME: return "resume";
  242. case OHCI_USB_OPER: return "operational";
  243. case OHCI_USB_SUSPEND: return "suspend";
  244. }
  245. return "?";
  246. }
  247. /* dump control and status registers */
  248. static void ohci_dump_status (ohci_t *controller)
  249. {
  250. struct ohci_regs *regs = controller->regs;
  251. __u32 temp;
  252. temp = readl (&regs->revision) & 0xff;
  253. if (temp != 0x10)
  254. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  255. temp = readl (&regs->control);
  256. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  257. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  258. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  259. (temp & OHCI_CTRL_IR) ? " IR" : "",
  260. hcfs2string (temp & OHCI_CTRL_HCFS),
  261. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  262. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  263. (temp & OHCI_CTRL_IE) ? " IE" : "",
  264. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  265. temp & OHCI_CTRL_CBSR
  266. );
  267. temp = readl (&regs->cmdstatus);
  268. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  269. (temp & OHCI_SOC) >> 16,
  270. (temp & OHCI_OCR) ? " OCR" : "",
  271. (temp & OHCI_BLF) ? " BLF" : "",
  272. (temp & OHCI_CLF) ? " CLF" : "",
  273. (temp & OHCI_HCR) ? " HCR" : ""
  274. );
  275. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  276. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  277. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  278. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  279. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  280. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  281. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  282. maybe_print_eds ("donehead", readl (&regs->donehead));
  283. }
  284. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  285. {
  286. __u32 temp, ndp, i;
  287. temp = roothub_a (controller);
  288. ndp = (temp & RH_A_NDP);
  289. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  290. ndp = (ndp == 2) ? 1:0;
  291. #endif
  292. if (verbose) {
  293. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  294. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  295. (temp & RH_A_NOCP) ? " NOCP" : "",
  296. (temp & RH_A_OCPM) ? " OCPM" : "",
  297. (temp & RH_A_DT) ? " DT" : "",
  298. (temp & RH_A_NPS) ? " NPS" : "",
  299. (temp & RH_A_PSM) ? " PSM" : "",
  300. ndp
  301. );
  302. temp = roothub_b (controller);
  303. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  304. temp,
  305. (temp & RH_B_PPCM) >> 16,
  306. (temp & RH_B_DR)
  307. );
  308. temp = roothub_status (controller);
  309. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  310. temp,
  311. (temp & RH_HS_CRWE) ? " CRWE" : "",
  312. (temp & RH_HS_OCIC) ? " OCIC" : "",
  313. (temp & RH_HS_LPSC) ? " LPSC" : "",
  314. (temp & RH_HS_DRWE) ? " DRWE" : "",
  315. (temp & RH_HS_OCI) ? " OCI" : "",
  316. (temp & RH_HS_LPS) ? " LPS" : ""
  317. );
  318. }
  319. for (i = 0; i < ndp; i++) {
  320. temp = roothub_portstatus (controller, i);
  321. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  322. i,
  323. temp,
  324. (temp & RH_PS_PRSC) ? " PRSC" : "",
  325. (temp & RH_PS_OCIC) ? " OCIC" : "",
  326. (temp & RH_PS_PSSC) ? " PSSC" : "",
  327. (temp & RH_PS_PESC) ? " PESC" : "",
  328. (temp & RH_PS_CSC) ? " CSC" : "",
  329. (temp & RH_PS_LSDA) ? " LSDA" : "",
  330. (temp & RH_PS_PPS) ? " PPS" : "",
  331. (temp & RH_PS_PRS) ? " PRS" : "",
  332. (temp & RH_PS_POCI) ? " POCI" : "",
  333. (temp & RH_PS_PSS) ? " PSS" : "",
  334. (temp & RH_PS_PES) ? " PES" : "",
  335. (temp & RH_PS_CCS) ? " CCS" : ""
  336. );
  337. }
  338. }
  339. static void ohci_dump (ohci_t *controller, int verbose)
  340. {
  341. dbg ("OHCI controller usb-%s state", controller->slot_name);
  342. /* dumps some of the state we know about */
  343. ohci_dump_status (controller);
  344. if (verbose)
  345. ep_print_int_eds (controller, "hcca");
  346. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  347. ohci_dump_roothub (controller, 1);
  348. }
  349. #endif /* DEBUG */
  350. /*-------------------------------------------------------------------------*
  351. * Interface functions (URB)
  352. *-------------------------------------------------------------------------*/
  353. /* get a transfer request */
  354. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  355. int transfer_len, struct devrequest *setup, int interval)
  356. {
  357. ohci_t *ohci;
  358. ed_t * ed;
  359. urb_priv_t *purb_priv;
  360. int i, size = 0;
  361. ohci = &gohci;
  362. /* when controller's hung, permit only roothub cleanup attempts
  363. * such as powering down ports */
  364. if (ohci->disabled) {
  365. err("sohci_submit_job: EPIPE");
  366. return -1;
  367. }
  368. #ifdef S3C24X0_merge
  369. /* if we have an unfinished URB from previous transaction let's
  370. * fail and scream as quickly as possible so as not to corrupt
  371. * further communication */
  372. if (!urb_finished) {
  373. err("sohci_submit_job: URB NOT FINISHED");
  374. return -1;
  375. }
  376. /* we're about to begin a new transaction here so mark the URB unfinished */
  377. urb_finished = 0;
  378. #endif
  379. /* every endpoint has a ed, locate and fill it */
  380. if (!(ed = ep_add_ed (dev, pipe))) {
  381. err("sohci_submit_job: ENOMEM");
  382. return -1;
  383. }
  384. /* for the private part of the URB we need the number of TDs (size) */
  385. switch (usb_pipetype (pipe)) {
  386. case PIPE_BULK: /* one TD for every 4096 Byte */
  387. size = (transfer_len - 1) / 4096 + 1;
  388. break;
  389. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  390. size = (transfer_len == 0)? 2:
  391. (transfer_len - 1) / 4096 + 3;
  392. break;
  393. }
  394. if (size >= (N_URB_TD - 1)) {
  395. err("need %d TDs, only have %d", size, N_URB_TD);
  396. return -1;
  397. }
  398. purb_priv = &urb_priv;
  399. purb_priv->pipe = pipe;
  400. /* fill the private part of the URB */
  401. purb_priv->length = size;
  402. purb_priv->ed = ed;
  403. purb_priv->actual_length = 0;
  404. /* allocate the TDs */
  405. /* note that td[0] was allocated in ep_add_ed */
  406. for (i = 0; i < size; i++) {
  407. purb_priv->td[i] = td_alloc (dev);
  408. if (!purb_priv->td[i]) {
  409. purb_priv->length = i;
  410. urb_free_priv (purb_priv);
  411. err("sohci_submit_job: ENOMEM");
  412. return -1;
  413. }
  414. }
  415. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  416. urb_free_priv (purb_priv);
  417. err("sohci_submit_job: EINVAL");
  418. return -1;
  419. }
  420. /* link the ed into a chain if is not already */
  421. if (ed->state != ED_OPER)
  422. ep_link (ohci, ed);
  423. /* fill the TDs and link it to the ed */
  424. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  425. return 0;
  426. }
  427. /*-------------------------------------------------------------------------*/
  428. #ifdef DEBUG
  429. /* tell us the current USB frame number */
  430. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  431. {
  432. ohci_t *ohci = &gohci;
  433. return m16_swap (ohci->hcca->frame_no);
  434. }
  435. #endif
  436. /*-------------------------------------------------------------------------*
  437. * ED handling functions
  438. *-------------------------------------------------------------------------*/
  439. /* link an ed into one of the HC chains */
  440. static int ep_link (ohci_t *ohci, ed_t *edi)
  441. {
  442. volatile ed_t *ed = edi;
  443. ed->state = ED_OPER;
  444. switch (ed->type) {
  445. case PIPE_CONTROL:
  446. ed->hwNextED = 0;
  447. if (ohci->ed_controltail == NULL) {
  448. writel (ed, &ohci->regs->ed_controlhead);
  449. } else {
  450. ohci->ed_controltail->hwNextED = m32_swap (ed);
  451. }
  452. ed->ed_prev = ohci->ed_controltail;
  453. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  454. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  455. ohci->hc_control |= OHCI_CTRL_CLE;
  456. writel (ohci->hc_control, &ohci->regs->control);
  457. }
  458. ohci->ed_controltail = edi;
  459. break;
  460. case PIPE_BULK:
  461. ed->hwNextED = 0;
  462. if (ohci->ed_bulktail == NULL) {
  463. writel (ed, &ohci->regs->ed_bulkhead);
  464. } else {
  465. ohci->ed_bulktail->hwNextED = m32_swap (ed);
  466. }
  467. ed->ed_prev = ohci->ed_bulktail;
  468. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  469. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  470. ohci->hc_control |= OHCI_CTRL_BLE;
  471. writel (ohci->hc_control, &ohci->regs->control);
  472. }
  473. ohci->ed_bulktail = edi;
  474. break;
  475. }
  476. return 0;
  477. }
  478. /*-------------------------------------------------------------------------*/
  479. /* unlink an ed from one of the HC chains.
  480. * just the link to the ed is unlinked.
  481. * the link from the ed still points to another operational ed or 0
  482. * so the HC can eventually finish the processing of the unlinked ed */
  483. static int ep_unlink (ohci_t *ohci, ed_t *edi)
  484. {
  485. volatile ed_t *ed = edi;
  486. ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
  487. switch (ed->type) {
  488. case PIPE_CONTROL:
  489. if (ed->ed_prev == NULL) {
  490. if (!ed->hwNextED) {
  491. ohci->hc_control &= ~OHCI_CTRL_CLE;
  492. writel (ohci->hc_control, &ohci->regs->control);
  493. }
  494. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  495. } else {
  496. ed->ed_prev->hwNextED = ed->hwNextED;
  497. }
  498. if (ohci->ed_controltail == ed) {
  499. ohci->ed_controltail = ed->ed_prev;
  500. } else {
  501. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  502. }
  503. break;
  504. case PIPE_BULK:
  505. if (ed->ed_prev == NULL) {
  506. if (!ed->hwNextED) {
  507. ohci->hc_control &= ~OHCI_CTRL_BLE;
  508. writel (ohci->hc_control, &ohci->regs->control);
  509. }
  510. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  511. } else {
  512. ed->ed_prev->hwNextED = ed->hwNextED;
  513. }
  514. if (ohci->ed_bulktail == ed) {
  515. ohci->ed_bulktail = ed->ed_prev;
  516. } else {
  517. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  518. }
  519. break;
  520. }
  521. ed->state = ED_UNLINK;
  522. return 0;
  523. }
  524. /*-------------------------------------------------------------------------*/
  525. /* add/reinit an endpoint; this should be done once at the
  526. * usb_set_configuration command, but the USB stack is a little bit
  527. * stateless so we do it at every transaction if the state of the ed
  528. * is ED_NEW then a dummy td is added and the state is changed to
  529. * ED_UNLINK in all other cases the state is left unchanged the ed
  530. * info fields are setted anyway even though most of them should not
  531. * change
  532. */
  533. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  534. {
  535. td_t *td;
  536. ed_t *ed_ret;
  537. volatile ed_t *ed;
  538. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  539. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  540. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  541. err("ep_add_ed: pending delete");
  542. /* pending delete request */
  543. return NULL;
  544. }
  545. if (ed->state == ED_NEW) {
  546. ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
  547. /* dummy td; end of td list for ed */
  548. td = td_alloc (usb_dev);
  549. ed->hwTailP = m32_swap (td);
  550. ed->hwHeadP = ed->hwTailP;
  551. ed->state = ED_UNLINK;
  552. ed->type = usb_pipetype (pipe);
  553. ohci_dev.ed_cnt++;
  554. }
  555. ed->hwINFO = m32_swap (usb_pipedevice (pipe)
  556. | usb_pipeendpoint (pipe) << 7
  557. | (usb_pipeisoc (pipe)? 0x8000: 0)
  558. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  559. | usb_pipeslow (pipe) << 13
  560. | usb_maxpacket (usb_dev, pipe) << 16);
  561. return ed_ret;
  562. }
  563. /*-------------------------------------------------------------------------*
  564. * TD handling functions
  565. *-------------------------------------------------------------------------*/
  566. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  567. static void td_fill (ohci_t *ohci, unsigned int info,
  568. void *data, int len,
  569. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  570. {
  571. volatile td_t *td, *td_pt;
  572. #ifdef OHCI_FILL_TRACE
  573. int i;
  574. #endif
  575. if (index > urb_priv->length) {
  576. err("index > length");
  577. return;
  578. }
  579. /* use this td as the next dummy */
  580. td_pt = urb_priv->td [index];
  581. td_pt->hwNextTD = 0;
  582. /* fill the old dummy TD */
  583. td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
  584. td->ed = urb_priv->ed;
  585. td->next_dl_td = NULL;
  586. td->index = index;
  587. td->data = (__u32)data;
  588. #ifdef OHCI_FILL_TRACE
  589. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  590. for (i = 0; i < len; i++)
  591. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  592. printf("\n");
  593. }
  594. #endif
  595. if (!len)
  596. data = 0;
  597. td->hwINFO = m32_swap (info);
  598. td->hwCBP = m32_swap (data);
  599. if (data)
  600. td->hwBE = m32_swap (data + len - 1);
  601. else
  602. td->hwBE = 0;
  603. td->hwNextTD = m32_swap (td_pt);
  604. #ifndef S3C24X0_merge
  605. td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
  606. #endif
  607. /* append to queue */
  608. td->ed->hwTailP = td->hwNextTD;
  609. }
  610. /*-------------------------------------------------------------------------*/
  611. /* prepare all TDs of a transfer */
  612. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  613. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  614. {
  615. ohci_t *ohci = &gohci;
  616. int data_len = transfer_len;
  617. void *data;
  618. int cnt = 0;
  619. __u32 info = 0;
  620. unsigned int toggle = 0;
  621. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  622. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  623. toggle = TD_T_TOGGLE;
  624. } else {
  625. toggle = TD_T_DATA0;
  626. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  627. }
  628. urb->td_cnt = 0;
  629. if (data_len)
  630. data = buffer;
  631. else
  632. data = 0;
  633. switch (usb_pipetype (pipe)) {
  634. case PIPE_BULK:
  635. info = usb_pipeout (pipe)?
  636. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  637. while(data_len > 4096) {
  638. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  639. data += 4096; data_len -= 4096; cnt++;
  640. }
  641. info = usb_pipeout (pipe)?
  642. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  643. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  644. cnt++;
  645. if (!ohci->sleeping)
  646. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  647. break;
  648. case PIPE_CONTROL:
  649. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  650. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  651. if (data_len > 0) {
  652. info = usb_pipeout (pipe)?
  653. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  654. /* NOTE: mishandles transfers >8K, some >4K */
  655. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  656. }
  657. info = usb_pipeout (pipe)?
  658. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  659. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  660. if (!ohci->sleeping)
  661. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  662. break;
  663. }
  664. if (urb->length != cnt)
  665. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  666. }
  667. /*-------------------------------------------------------------------------*
  668. * Done List handling functions
  669. *-------------------------------------------------------------------------*/
  670. /* calculate the transfer length and update the urb */
  671. static void dl_transfer_length(td_t * td)
  672. {
  673. __u32 tdINFO, tdBE, tdCBP;
  674. urb_priv_t *lurb_priv = &urb_priv;
  675. tdINFO = m32_swap (td->hwINFO);
  676. tdBE = m32_swap (td->hwBE);
  677. tdCBP = m32_swap (td->hwCBP);
  678. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  679. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  680. if (tdBE != 0) {
  681. if (td->hwCBP == 0)
  682. lurb_priv->actual_length += tdBE - td->data + 1;
  683. else
  684. lurb_priv->actual_length += tdCBP - td->data;
  685. }
  686. }
  687. }
  688. /*-------------------------------------------------------------------------*/
  689. /* replies to the request have to be on a FIFO basis so
  690. * we reverse the reversed done-list */
  691. static td_t * dl_reverse_done_list (ohci_t *ohci)
  692. {
  693. __u32 td_list_hc;
  694. td_t *td_rev = NULL;
  695. td_t *td_list = NULL;
  696. urb_priv_t *lurb_priv = NULL;
  697. td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
  698. ohci->hcca->done_head = 0;
  699. while (td_list_hc) {
  700. td_list = (td_t *)td_list_hc;
  701. if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
  702. lurb_priv = &urb_priv;
  703. dbg(" USB-error/status: %x : %p",
  704. TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
  705. if (td_list->ed->hwHeadP & m32_swap (0x1)) {
  706. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  707. td_list->ed->hwHeadP =
  708. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
  709. (td_list->ed->hwHeadP & m32_swap (0x2));
  710. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  711. } else
  712. td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
  713. }
  714. #ifdef CONFIG_MPC5200
  715. td_list->hwNextTD = 0;
  716. #endif
  717. }
  718. td_list->next_dl_td = td_rev;
  719. td_rev = td_list;
  720. td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
  721. }
  722. return td_list;
  723. }
  724. /*-------------------------------------------------------------------------*/
  725. /* td done list */
  726. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  727. {
  728. td_t *td_list_next = NULL;
  729. ed_t *ed;
  730. int cc = 0;
  731. int stat = 0;
  732. /* urb_t *urb; */
  733. urb_priv_t *lurb_priv;
  734. __u32 tdINFO, edHeadP, edTailP;
  735. while (td_list) {
  736. td_list_next = td_list->next_dl_td;
  737. lurb_priv = &urb_priv;
  738. tdINFO = m32_swap (td_list->hwINFO);
  739. ed = td_list->ed;
  740. dl_transfer_length(td_list);
  741. /* error code of transfer */
  742. cc = TD_CC_GET (tdINFO);
  743. if (cc != 0) {
  744. dbg("ConditionCode %#x", cc);
  745. stat = cc_to_error[cc];
  746. }
  747. #ifdef S3C24X0_merge
  748. /* see if this done list makes for all TD's of current URB,
  749. * and mark the URB finished if so */
  750. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  751. if ((ed->state & (ED_OPER | ED_UNLINK)))
  752. urb_finished = 1;
  753. else
  754. dbg("dl_done_list: strange.., ED state %x, ed->state\n");
  755. } else
  756. dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
  757. lurb_priv->length);
  758. #endif
  759. if (ed->state != ED_NEW) {
  760. edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
  761. edTailP = m32_swap (ed->hwTailP);
  762. /* unlink eds if they are not busy */
  763. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  764. ep_unlink (ohci, ed);
  765. }
  766. td_list = td_list_next;
  767. }
  768. return stat;
  769. }
  770. /*-------------------------------------------------------------------------*
  771. * Virtual Root Hub
  772. *-------------------------------------------------------------------------*/
  773. /* Device descriptor */
  774. static __u8 root_hub_dev_des[] =
  775. {
  776. 0x12, /* __u8 bLength; */
  777. 0x01, /* __u8 bDescriptorType; Device */
  778. 0x10, /* __u16 bcdUSB; v1.1 */
  779. 0x01,
  780. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  781. 0x00, /* __u8 bDeviceSubClass; */
  782. 0x00, /* __u8 bDeviceProtocol; */
  783. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  784. 0x00, /* __u16 idVendor; */
  785. 0x00,
  786. 0x00, /* __u16 idProduct; */
  787. 0x00,
  788. 0x00, /* __u16 bcdDevice; */
  789. 0x00,
  790. 0x00, /* __u8 iManufacturer; */
  791. 0x01, /* __u8 iProduct; */
  792. 0x00, /* __u8 iSerialNumber; */
  793. 0x01 /* __u8 bNumConfigurations; */
  794. };
  795. /* Configuration descriptor */
  796. static __u8 root_hub_config_des[] =
  797. {
  798. 0x09, /* __u8 bLength; */
  799. 0x02, /* __u8 bDescriptorType; Configuration */
  800. 0x19, /* __u16 wTotalLength; */
  801. 0x00,
  802. 0x01, /* __u8 bNumInterfaces; */
  803. 0x01, /* __u8 bConfigurationValue; */
  804. 0x00, /* __u8 iConfiguration; */
  805. 0x40, /* __u8 bmAttributes;
  806. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  807. 0x00, /* __u8 MaxPower; */
  808. /* interface */
  809. 0x09, /* __u8 if_bLength; */
  810. 0x04, /* __u8 if_bDescriptorType; Interface */
  811. 0x00, /* __u8 if_bInterfaceNumber; */
  812. 0x00, /* __u8 if_bAlternateSetting; */
  813. 0x01, /* __u8 if_bNumEndpoints; */
  814. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  815. 0x00, /* __u8 if_bInterfaceSubClass; */
  816. 0x00, /* __u8 if_bInterfaceProtocol; */
  817. 0x00, /* __u8 if_iInterface; */
  818. /* endpoint */
  819. 0x07, /* __u8 ep_bLength; */
  820. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  821. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  822. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  823. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  824. 0x00,
  825. 0xff /* __u8 ep_bInterval; 255 ms */
  826. };
  827. static unsigned char root_hub_str_index0[] =
  828. {
  829. 0x04, /* __u8 bLength; */
  830. 0x03, /* __u8 bDescriptorType; String-descriptor */
  831. 0x09, /* __u8 lang ID */
  832. 0x04, /* __u8 lang ID */
  833. };
  834. static unsigned char root_hub_str_index1[] =
  835. {
  836. 28, /* __u8 bLength; */
  837. 0x03, /* __u8 bDescriptorType; String-descriptor */
  838. 'O', /* __u8 Unicode */
  839. 0, /* __u8 Unicode */
  840. 'H', /* __u8 Unicode */
  841. 0, /* __u8 Unicode */
  842. 'C', /* __u8 Unicode */
  843. 0, /* __u8 Unicode */
  844. 'I', /* __u8 Unicode */
  845. 0, /* __u8 Unicode */
  846. ' ', /* __u8 Unicode */
  847. 0, /* __u8 Unicode */
  848. 'R', /* __u8 Unicode */
  849. 0, /* __u8 Unicode */
  850. 'o', /* __u8 Unicode */
  851. 0, /* __u8 Unicode */
  852. 'o', /* __u8 Unicode */
  853. 0, /* __u8 Unicode */
  854. 't', /* __u8 Unicode */
  855. 0, /* __u8 Unicode */
  856. ' ', /* __u8 Unicode */
  857. 0, /* __u8 Unicode */
  858. 'H', /* __u8 Unicode */
  859. 0, /* __u8 Unicode */
  860. 'u', /* __u8 Unicode */
  861. 0, /* __u8 Unicode */
  862. 'b', /* __u8 Unicode */
  863. 0, /* __u8 Unicode */
  864. };
  865. /* Hub class-specific descriptor is constructed dynamically */
  866. /*-------------------------------------------------------------------------*/
  867. #define OK(x) len = (x); break
  868. #ifdef DEBUG
  869. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  870. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  871. #else
  872. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  873. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  874. #endif
  875. #define RD_RH_STAT roothub_status(&gohci)
  876. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  877. /* request to virtual root hub */
  878. int rh_check_port_status(ohci_t *controller)
  879. {
  880. __u32 temp, ndp, i;
  881. int res;
  882. res = -1;
  883. temp = roothub_a (controller);
  884. ndp = (temp & RH_A_NDP);
  885. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  886. ndp = (ndp == 2) ? 1:0;
  887. #endif
  888. for (i = 0; i < ndp; i++) {
  889. temp = roothub_portstatus (controller, i);
  890. /* check for a device disconnect */
  891. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  892. (RH_PS_PESC | RH_PS_CSC)) &&
  893. ((temp & RH_PS_CCS) == 0)) {
  894. res = i;
  895. break;
  896. }
  897. }
  898. return res;
  899. }
  900. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  901. void *buffer, int transfer_len, struct devrequest *cmd)
  902. {
  903. void * data = buffer;
  904. int leni = transfer_len;
  905. int len = 0;
  906. int stat = 0;
  907. __u32 datab[4];
  908. __u8 *data_buf = (__u8 *)datab;
  909. __u16 bmRType_bReq;
  910. __u16 wValue;
  911. __u16 wIndex;
  912. __u16 wLength;
  913. #ifdef DEBUG
  914. urb_priv.actual_length = 0;
  915. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  916. #else
  917. wait_ms(1);
  918. #endif
  919. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  920. info("Root-Hub submit IRQ: NOT implemented");
  921. return 0;
  922. }
  923. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  924. wValue = m16_swap (cmd->value);
  925. wIndex = m16_swap (cmd->index);
  926. wLength = m16_swap (cmd->length);
  927. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  928. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  929. switch (bmRType_bReq) {
  930. /* Request Destination:
  931. without flags: Device,
  932. RH_INTERFACE: interface,
  933. RH_ENDPOINT: endpoint,
  934. RH_CLASS means HUB here,
  935. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  936. */
  937. case RH_GET_STATUS:
  938. *(__u16 *) data_buf = m16_swap (1); OK (2);
  939. case RH_GET_STATUS | RH_INTERFACE:
  940. *(__u16 *) data_buf = m16_swap (0); OK (2);
  941. case RH_GET_STATUS | RH_ENDPOINT:
  942. *(__u16 *) data_buf = m16_swap (0); OK (2);
  943. case RH_GET_STATUS | RH_CLASS:
  944. *(__u32 *) data_buf = m32_swap (
  945. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  946. OK (4);
  947. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  948. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  949. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  950. switch (wValue) {
  951. case (RH_ENDPOINT_STALL): OK (0);
  952. }
  953. break;
  954. case RH_CLEAR_FEATURE | RH_CLASS:
  955. switch (wValue) {
  956. case RH_C_HUB_LOCAL_POWER:
  957. OK(0);
  958. case (RH_C_HUB_OVER_CURRENT):
  959. WR_RH_STAT(RH_HS_OCIC); OK (0);
  960. }
  961. break;
  962. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  963. switch (wValue) {
  964. case (RH_PORT_ENABLE):
  965. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  966. case (RH_PORT_SUSPEND):
  967. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  968. case (RH_PORT_POWER):
  969. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  970. case (RH_C_PORT_CONNECTION):
  971. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  972. case (RH_C_PORT_ENABLE):
  973. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  974. case (RH_C_PORT_SUSPEND):
  975. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  976. case (RH_C_PORT_OVER_CURRENT):
  977. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  978. case (RH_C_PORT_RESET):
  979. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  980. }
  981. break;
  982. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  983. switch (wValue) {
  984. case (RH_PORT_SUSPEND):
  985. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  986. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  987. if (RD_RH_PORTSTAT & RH_PS_CCS)
  988. WR_RH_PORTSTAT (RH_PS_PRS);
  989. OK (0);
  990. case (RH_PORT_POWER):
  991. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  992. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  993. if (RD_RH_PORTSTAT & RH_PS_CCS)
  994. WR_RH_PORTSTAT (RH_PS_PES );
  995. OK (0);
  996. }
  997. break;
  998. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  999. case RH_GET_DESCRIPTOR:
  1000. switch ((wValue & 0xff00) >> 8) {
  1001. case (0x01): /* device descriptor */
  1002. len = min_t(unsigned int,
  1003. leni,
  1004. min_t(unsigned int,
  1005. sizeof (root_hub_dev_des),
  1006. wLength));
  1007. data_buf = root_hub_dev_des; OK(len);
  1008. case (0x02): /* configuration descriptor */
  1009. len = min_t(unsigned int,
  1010. leni,
  1011. min_t(unsigned int,
  1012. sizeof (root_hub_config_des),
  1013. wLength));
  1014. data_buf = root_hub_config_des; OK(len);
  1015. case (0x03): /* string descriptors */
  1016. if(wValue==0x0300) {
  1017. len = min_t(unsigned int,
  1018. leni,
  1019. min_t(unsigned int,
  1020. sizeof (root_hub_str_index0),
  1021. wLength));
  1022. data_buf = root_hub_str_index0;
  1023. OK(len);
  1024. }
  1025. if(wValue==0x0301) {
  1026. len = min_t(unsigned int,
  1027. leni,
  1028. min_t(unsigned int,
  1029. sizeof (root_hub_str_index1),
  1030. wLength));
  1031. data_buf = root_hub_str_index1;
  1032. OK(len);
  1033. }
  1034. default:
  1035. stat = USB_ST_STALLED;
  1036. }
  1037. break;
  1038. case RH_GET_DESCRIPTOR | RH_CLASS:
  1039. {
  1040. __u32 temp = roothub_a (&gohci);
  1041. data_buf [0] = 9; /* min length; */
  1042. data_buf [1] = 0x29;
  1043. data_buf [2] = temp & RH_A_NDP;
  1044. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1045. data_buf [2] = (data_buf [2] == 2) ? 1:0;
  1046. #endif
  1047. data_buf [3] = 0;
  1048. if (temp & RH_A_PSM) /* per-port power switching? */
  1049. data_buf [3] |= 0x1;
  1050. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1051. data_buf [3] |= 0x10;
  1052. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  1053. data_buf [3] |= 0x8;
  1054. /* corresponds to data_buf[4-7] */
  1055. datab [1] = 0;
  1056. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1057. temp = roothub_b (&gohci);
  1058. data_buf [7] = temp & RH_B_DR;
  1059. if (data_buf [2] < 7) {
  1060. data_buf [8] = 0xff;
  1061. } else {
  1062. data_buf [0] += 2;
  1063. data_buf [8] = (temp & RH_B_DR) >> 8;
  1064. data_buf [10] = data_buf [9] = 0xff;
  1065. }
  1066. len = min_t(unsigned int, leni,
  1067. min_t(unsigned int, data_buf [0], wLength));
  1068. OK (len);
  1069. }
  1070. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1071. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1072. default:
  1073. dbg ("unsupported root hub command");
  1074. stat = USB_ST_STALLED;
  1075. }
  1076. #ifdef DEBUG
  1077. ohci_dump_roothub (&gohci, 1);
  1078. #else
  1079. wait_ms(1);
  1080. #endif
  1081. len = min_t(int, len, leni);
  1082. if (data != data_buf)
  1083. memcpy (data, data_buf, len);
  1084. dev->act_len = len;
  1085. dev->status = stat;
  1086. #ifdef DEBUG
  1087. if (transfer_len)
  1088. urb_priv.actual_length = transfer_len;
  1089. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1090. #else
  1091. wait_ms(1);
  1092. #endif
  1093. return stat;
  1094. }
  1095. /*-------------------------------------------------------------------------*/
  1096. /* common code for handling submit messages - used for all but root hub */
  1097. /* accesses. */
  1098. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1099. int transfer_len, struct devrequest *setup, int interval)
  1100. {
  1101. int stat = 0;
  1102. int maxsize = usb_maxpacket(dev, pipe);
  1103. int timeout;
  1104. /* device pulled? Shortcut the action. */
  1105. if (devgone == dev) {
  1106. dev->status = USB_ST_CRC_ERR;
  1107. return 0;
  1108. }
  1109. #ifdef DEBUG
  1110. urb_priv.actual_length = 0;
  1111. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1112. #else
  1113. wait_ms(1);
  1114. #endif
  1115. if (!maxsize) {
  1116. err("submit_common_message: pipesize for pipe %lx is zero",
  1117. pipe);
  1118. return -1;
  1119. }
  1120. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1121. err("sohci_submit_job failed");
  1122. return -1;
  1123. }
  1124. wait_ms(10);
  1125. /* ohci_dump_status(&gohci); */
  1126. /* allow more time for a BULK device to react - some are slow */
  1127. #define BULK_TO 5000 /* timeout in milliseconds */
  1128. if (usb_pipetype (pipe) == PIPE_BULK)
  1129. timeout = BULK_TO;
  1130. else
  1131. timeout = 100;
  1132. /* wait for it to complete */
  1133. for (;;) {
  1134. /* check whether the controller is done */
  1135. stat = hc_interrupt();
  1136. if (stat < 0) {
  1137. stat = USB_ST_CRC_ERR;
  1138. break;
  1139. }
  1140. #ifdef S3C24X0_merge
  1141. /* NOTE: since we are not interrupt driven in U-Boot and always
  1142. * handle only one URB at a time, we cannot assume the
  1143. * transaction finished on the first successful return from
  1144. * hc_interrupt().. unless the flag for current URB is set,
  1145. * meaning that all TD's to/from device got actually
  1146. * transferred and processed. If the current URB is not
  1147. * finished we need to re-iterate this loop so as
  1148. * hc_interrupt() gets called again as there needs to be some
  1149. * more TD's to process still */
  1150. if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
  1151. #else
  1152. if (stat >= 0 && stat != 0xff) {
  1153. #endif
  1154. /* 0xff is returned for an SF-interrupt */
  1155. break;
  1156. }
  1157. if (--timeout) {
  1158. wait_ms(1);
  1159. } else {
  1160. err("CTL:TIMEOUT ");
  1161. #ifdef S3C24X0_merge
  1162. dbg("submit_common_msg: TO status %x\n", stat);
  1163. urb_finished = 1;
  1164. #endif
  1165. stat = USB_ST_CRC_ERR;
  1166. break;
  1167. }
  1168. }
  1169. #ifndef S3C24X0_merge
  1170. /* we got an Root Hub Status Change interrupt */
  1171. if (got_rhsc) {
  1172. #ifdef DEBUG
  1173. ohci_dump_roothub (&gohci, 1);
  1174. #endif
  1175. got_rhsc = 0;
  1176. /* abuse timeout */
  1177. timeout = rh_check_port_status(&gohci);
  1178. if (timeout >= 0) {
  1179. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1180. /* the called routine adds 1 to the passed value */
  1181. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1182. #endif
  1183. /*
  1184. * XXX
  1185. * This is potentially dangerous because it assumes
  1186. * that only one device is ever plugged in!
  1187. */
  1188. devgone = dev;
  1189. }
  1190. }
  1191. #endif /* S3C24X0_merge */
  1192. dev->status = stat;
  1193. dev->act_len = transfer_len;
  1194. #ifdef DEBUG
  1195. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1196. #else
  1197. wait_ms(1);
  1198. #endif
  1199. /* free TDs in urb_priv */
  1200. urb_free_priv (&urb_priv);
  1201. return 0;
  1202. }
  1203. /* submit routines called from usb.c */
  1204. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1205. int transfer_len)
  1206. {
  1207. info("submit_bulk_msg");
  1208. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1209. }
  1210. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1211. int transfer_len, struct devrequest *setup)
  1212. {
  1213. int maxsize = usb_maxpacket(dev, pipe);
  1214. info("submit_control_msg");
  1215. #ifdef DEBUG
  1216. urb_priv.actual_length = 0;
  1217. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1218. #else
  1219. wait_ms(1);
  1220. #endif
  1221. if (!maxsize) {
  1222. err("submit_control_message: pipesize for pipe %lx is zero",
  1223. pipe);
  1224. return -1;
  1225. }
  1226. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1227. gohci.rh.dev = dev;
  1228. /* root hub - redirect */
  1229. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1230. setup);
  1231. }
  1232. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1233. }
  1234. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1235. int transfer_len, int interval)
  1236. {
  1237. info("submit_int_msg");
  1238. return -1;
  1239. }
  1240. /*-------------------------------------------------------------------------*
  1241. * HC functions
  1242. *-------------------------------------------------------------------------*/
  1243. /* reset the HC and BUS */
  1244. static int hc_reset (ohci_t *ohci)
  1245. {
  1246. int timeout = 30;
  1247. int smm_timeout = 50; /* 0,5 sec */
  1248. dbg("%s\n", __FUNCTION__);
  1249. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1250. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1251. info("USB HC TakeOver from SMM");
  1252. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1253. wait_ms (10);
  1254. if (--smm_timeout == 0) {
  1255. err("USB HC TakeOver failed!");
  1256. return -1;
  1257. }
  1258. }
  1259. }
  1260. /* Disable HC interrupts */
  1261. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1262. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
  1263. ohci->slot_name,
  1264. readl(&ohci->regs->control));
  1265. /* Reset USB (needed by some controllers) */
  1266. ohci->hc_control = 0;
  1267. writel (ohci->hc_control, &ohci->regs->control);
  1268. /* HC Reset requires max 10 us delay */
  1269. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1270. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1271. if (--timeout == 0) {
  1272. err("USB HC reset timed out!");
  1273. return -1;
  1274. }
  1275. udelay (1);
  1276. }
  1277. return 0;
  1278. }
  1279. /*-------------------------------------------------------------------------*/
  1280. /* Start an OHCI controller, set the BUS operational
  1281. * enable interrupts
  1282. * connect the virtual root hub */
  1283. static int hc_start (ohci_t * ohci)
  1284. {
  1285. __u32 mask;
  1286. unsigned int fminterval;
  1287. ohci->disabled = 1;
  1288. /* Tell the controller where the control and bulk lists are
  1289. * The lists are empty now. */
  1290. writel (0, &ohci->regs->ed_controlhead);
  1291. writel (0, &ohci->regs->ed_bulkhead);
  1292. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1293. fminterval = 0x2edf;
  1294. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1295. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1296. writel (fminterval, &ohci->regs->fminterval);
  1297. writel (0x628, &ohci->regs->lsthresh);
  1298. /* start controller operations */
  1299. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1300. ohci->disabled = 0;
  1301. writel (ohci->hc_control, &ohci->regs->control);
  1302. /* disable all interrupts */
  1303. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1304. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1305. OHCI_INTR_OC | OHCI_INTR_MIE);
  1306. writel (mask, &ohci->regs->intrdisable);
  1307. /* clear all interrupts */
  1308. mask &= ~OHCI_INTR_MIE;
  1309. writel (mask, &ohci->regs->intrstatus);
  1310. /* Choose the interrupts we care about now - but w/o MIE */
  1311. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1312. writel (mask, &ohci->regs->intrenable);
  1313. #ifdef OHCI_USE_NPS
  1314. /* required for AMD-756 and some Mac platforms */
  1315. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1316. &ohci->regs->roothub.a);
  1317. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1318. #endif /* OHCI_USE_NPS */
  1319. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1320. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1321. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1322. /* connect the virtual root hub */
  1323. ohci->rh.devnum = 0;
  1324. return 0;
  1325. }
  1326. /*-------------------------------------------------------------------------*/
  1327. /* an interrupt happens */
  1328. static int hc_interrupt (void)
  1329. {
  1330. ohci_t *ohci = &gohci;
  1331. struct ohci_regs *regs = ohci->regs;
  1332. int ints;
  1333. int stat = -1;
  1334. #ifdef S3C24X0_merge
  1335. if ((ohci->hcca->done_head != 0) &&
  1336. !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1337. ints = OHCI_INTR_WDH;
  1338. } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
  1339. ohci->disabled++;
  1340. err ("%s device removed!", ohci->slot_name);
  1341. return -1;
  1342. } else if ((ints &= readl (&regs->intrenable)) == 0) {
  1343. dbg("hc_interrupt: returning..\n");
  1344. return 0xff;
  1345. }
  1346. #else
  1347. if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1348. ints = OHCI_INTR_WDH;
  1349. } else {
  1350. ints = readl (&regs->intrstatus);
  1351. }
  1352. #endif
  1353. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1354. if (ints & OHCI_INTR_RHSC) {
  1355. got_rhsc = 1;
  1356. #ifdef S3C24X0_merge
  1357. stat = 0xff;
  1358. #endif
  1359. }
  1360. if (ints & OHCI_INTR_UE) {
  1361. ohci->disabled++;
  1362. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1363. ohci->slot_name);
  1364. /* e.g. due to PCI Master/Target Abort */
  1365. #ifdef DEBUG
  1366. ohci_dump (ohci, 1);
  1367. #else
  1368. wait_ms(1);
  1369. #endif
  1370. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1371. /* Make some non-interrupt context restart the controller. */
  1372. /* Count and limit the retries though; either hardware or */
  1373. /* software errors can go forever... */
  1374. hc_reset (ohci);
  1375. return -1;
  1376. }
  1377. if (ints & OHCI_INTR_WDH) {
  1378. wait_ms(1);
  1379. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1380. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1381. writel (OHCI_INTR_WDH, &regs->intrenable);
  1382. }
  1383. if (ints & OHCI_INTR_SO) {
  1384. dbg("USB Schedule overrun\n");
  1385. writel (OHCI_INTR_SO, &regs->intrenable);
  1386. stat = -1;
  1387. }
  1388. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1389. if (ints & OHCI_INTR_SF) {
  1390. unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
  1391. wait_ms(1);
  1392. writel (OHCI_INTR_SF, &regs->intrdisable);
  1393. if (ohci->ed_rm_list[frame] != NULL)
  1394. writel (OHCI_INTR_SF, &regs->intrenable);
  1395. stat = 0xff;
  1396. }
  1397. writel (ints, &regs->intrstatus);
  1398. return stat;
  1399. }
  1400. /*-------------------------------------------------------------------------*/
  1401. /*-------------------------------------------------------------------------*/
  1402. /* De-allocate all resources.. */
  1403. static void hc_release_ohci (ohci_t *ohci)
  1404. {
  1405. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1406. if (!ohci->disabled)
  1407. hc_reset (ohci);
  1408. }
  1409. /*-------------------------------------------------------------------------*/
  1410. /*
  1411. * low level initalisation routine, called from usb.c
  1412. */
  1413. static char ohci_inited = 0;
  1414. int usb_lowlevel_init(void)
  1415. {
  1416. #ifdef CFG_USB_OHCI_CPU_INIT
  1417. /* cpu dependant init */
  1418. if(usb_cpu_init())
  1419. return -1;
  1420. #endif
  1421. #ifdef CFG_USB_OHCI_BOARD_INIT
  1422. /* board dependant init */
  1423. if(usb_board_init())
  1424. return -1;
  1425. #endif
  1426. memset (&gohci, 0, sizeof (ohci_t));
  1427. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1428. /* align the storage */
  1429. if ((__u32)&ghcca[0] & 0xff) {
  1430. err("HCCA not aligned!!");
  1431. return -1;
  1432. }
  1433. phcca = &ghcca[0];
  1434. info("aligned ghcca %p", phcca);
  1435. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1436. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1437. err("EDs not aligned!!");
  1438. return -1;
  1439. }
  1440. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1441. if ((__u32)gtd & 0x7) {
  1442. err("TDs not aligned!!");
  1443. return -1;
  1444. }
  1445. ptd = gtd;
  1446. gohci.hcca = phcca;
  1447. memset (phcca, 0, sizeof (struct ohci_hcca));
  1448. gohci.disabled = 1;
  1449. gohci.sleeping = 0;
  1450. gohci.irq = -1;
  1451. gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
  1452. gohci.flags = 0;
  1453. gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
  1454. if (hc_reset (&gohci) < 0) {
  1455. hc_release_ohci (&gohci);
  1456. err ("can't reset usb-%s", gohci.slot_name);
  1457. #ifdef CFG_USB_OHCI_BOARD_INIT
  1458. /* board dependant cleanup */
  1459. usb_board_init_fail();
  1460. #endif
  1461. #ifdef CFG_USB_OHCI_CPU_INIT
  1462. /* cpu dependant cleanup */
  1463. usb_cpu_init_fail();
  1464. #endif
  1465. return -1;
  1466. }
  1467. /* FIXME this is a second HC reset; why?? */
  1468. /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
  1469. wait_ms(10); */
  1470. if (hc_start (&gohci) < 0) {
  1471. err ("can't start usb-%s", gohci.slot_name);
  1472. hc_release_ohci (&gohci);
  1473. /* Initialization failed */
  1474. #ifdef CFG_USB_OHCI_BOARD_INIT
  1475. /* board dependant cleanup */
  1476. usb_board_stop();
  1477. #endif
  1478. #ifdef CFG_USB_OHCI_CPU_INIT
  1479. /* cpu dependant cleanup */
  1480. usb_cpu_stop();
  1481. #endif
  1482. return -1;
  1483. }
  1484. #ifdef DEBUG
  1485. ohci_dump (&gohci, 1);
  1486. #else
  1487. wait_ms(1);
  1488. # ifdef S3C24X0_merge
  1489. urb_finished = 1;
  1490. # endif
  1491. #endif
  1492. ohci_inited = 1;
  1493. return 0;
  1494. }
  1495. int usb_lowlevel_stop(void)
  1496. {
  1497. /* this gets called really early - before the controller has */
  1498. /* even been initialized! */
  1499. if (!ohci_inited)
  1500. return 0;
  1501. /* TODO release any interrupts, etc. */
  1502. /* call hc_release_ohci() here ? */
  1503. hc_reset (&gohci);
  1504. #ifdef CFG_USB_OHCI_BOARD_INIT
  1505. /* board dependant cleanup */
  1506. if(usb_board_stop())
  1507. return -1;
  1508. #endif
  1509. #ifdef CFG_USB_OHCI_CPU_INIT
  1510. /* cpu dependant cleanup */
  1511. if(usb_cpu_stop())
  1512. return -1;
  1513. #endif
  1514. return 0;
  1515. }
  1516. #endif /* CONFIG_USB_OHCI */