multiverse.h 4.0 KB

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  1. /*
  2. * multiverse.h
  3. *
  4. * VME driver for Multiverse
  5. *
  6. * Author : Sangmoon Kim
  7. * dogoil@etinsys.com
  8. *
  9. * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. */
  16. #ifndef __MULTIVERSE_H__
  17. #define __MULTIVERSE_H__
  18. #define VME_A32_MSTR_BUS 0x90000000
  19. #define VME_A32_MSTR_SIZE 0x01000000
  20. #define VME_A32_SLV_SIZE 0x01000000
  21. #define VME_A32_SLV_BUS 0x90000000
  22. #define VME_A24_SLV_BUS 0x00000000
  23. #define VME_A16_SLV_BUS 0x00000000
  24. #define VME_A32_SLV_LOCAL 0x00000000
  25. #define VME_A24_SLV_LOCAL 0x00000000
  26. #define VME_A16_SLV_LOCAL 0x00000000
  27. #define A32_SLV_WINDOW
  28. #undef A24_SLV_WINDOW
  29. #undef A16_SLV_WINDOW
  30. #undef REG_SLV_WINDOW
  31. /* PCI Registers */
  32. #define P_IMG_CTRL0 0x100
  33. #define P_BA0 0x104
  34. #define P_AM0 0x108
  35. #define P_TA0 0x10C
  36. #define P_IMG_CTRL1 0x110
  37. #define P_BA1 0x114
  38. #define P_AM1 0x118
  39. #define P_TA1 0x11C
  40. #define P_IMG_CTRL2 0x120
  41. #define P_BA2 0x124
  42. #define P_AM2 0x128
  43. #define P_TA2 0x12C
  44. #define P_IMG_CTRL3 0x130
  45. #define P_BA3 0x134
  46. #define P_AM3 0x138
  47. #define P_TA3 0x13C
  48. #define P_IMG_CTRL4 0x140
  49. #define P_BA4 0x144
  50. #define P_AM4 0x148
  51. #define P_TA4 0x14C
  52. #define P_IMG_CTRL5 0x150
  53. #define P_BA5 0x154
  54. #define P_AM5 0x158
  55. #define P_TA5 0x15C
  56. #define P_ERR_CS 0x160
  57. #define P_ERR_ADDR 0x164
  58. #define P_ERR_DATA 0x168
  59. #define WB_CONF_SPC_BAR 0x180
  60. #define W_IMG_CTRL1 0x184
  61. #define W_BA1 0x188
  62. #define W_AM1 0x18C
  63. #define W_TA1 0x190
  64. #define W_IMG_CTRL2 0x194
  65. #define W_BA2 0x198
  66. #define W_AM2 0x19C
  67. #define W_TA2 0x1A0
  68. #define W_IMG_CTRL3 0x1A4
  69. #define W_BA3 0x1A8
  70. #define W_AM3 0x1AC
  71. #define W_TA3 0x1B0
  72. #define W_IMG_CTRL4 0x1B4
  73. #define W_BA4 0x1B8
  74. #define W_AM4 0x1BC
  75. #define W_TA4 0x1C0
  76. #define W_IMG_CTRL5 0x1C4
  77. #define W_BA5 0x1C8
  78. #define W_AM5 0x1CC
  79. #define W_TA5 0x1D0
  80. #define W_ERR_CS 0x1D4
  81. #define W_ERR_ADDR 0x1D8
  82. #define W_ERR_DATA 0x1DC
  83. #define CNF_ADDR 0x1E0
  84. #define CNF_DATA 0x1E4
  85. #define INT_ACK 0x1E8
  86. #define ICR 0x1EC
  87. #define ISR 0x1F0
  88. /* VME registers */
  89. #define VME_SLAVE32_AM 0x03
  90. #define VME_SLAVE24_AM 0x02
  91. #define VME_SLAVE16_AM 0x01
  92. #define VME_SLAVE_REG_AM 0x00
  93. #define VME_SLAVE32_A 0x07
  94. #define VME_SLAVE24_A 0x06
  95. #define VME_SLAVE16_A 0x05
  96. #define VME_SLAVE_REG_A 0x04
  97. #define VME_SLAVE32_MASK 0x0B
  98. #define VME_SLAVE24_MASK 0x0A
  99. #define VME_SLAVE16_MASK 0x09
  100. #define VME_SLAVE_REG_MASK 0x08
  101. #define VME_SLAVE32_EN 0x0F
  102. #define VME_SLAVE24_EN 0x0E
  103. #define VME_SLAVE16_EN 0x0D
  104. #define VME_SLAVE_REG_EN 0x0C
  105. #define VME_MASTER32_AM 0x13
  106. #define VME_MASTER24_AM 0x12
  107. #define VME_MASTER16_AM 0x11
  108. #define VME_MASTER_REG_AM 0x10
  109. #define VME_RMW_ADRS 0x14
  110. #define VME_MBOX 0x18
  111. #define VME_STATUS 0x1E
  112. #define VME_CTRL 0x1C
  113. #define VME_IRQ 0x20
  114. #define VME_INT_EN 0x21
  115. #define VME_INT 0x22
  116. #define VME_IRQ1_REG 0x24
  117. #define VME_IRQ2_REG 0x28
  118. #define VME_IRQ3_REG 0x2C
  119. #define VME_IRQ4_REG 0x30
  120. #define VME_IRQ5_REG 0x34
  121. #define VME_IRQ6_REG 0x38
  122. #define VME_IRQ7_REG 0x3C
  123. /* VME control register */
  124. #define VME_CTRL_BRDRST 0x01
  125. #define VME_CTRL_SYSRST 0x02
  126. #define VME_CTRL_RMW 0x04
  127. #define VME_CTRL_SHORT_D 0x08
  128. #define VME_CTRL_SYSFAIL 0x10
  129. #define VME_CTRL_VOWN 0x20
  130. #define VME_CTRL_A16_REG_MODE 0x40
  131. /* VME status register */
  132. #define VME_STATUS_SYSCON 0x01
  133. #define VME_STATUS_SYSFAIL 0x02
  134. #define VME_STATUS_ACFAIL 0x04
  135. #define VME_STATUS_SYSRST 0x08
  136. #define VME_STATUS_VOWN 0x10
  137. /* Interrupt types */
  138. #define LVL1 0x0002
  139. #define LVL2 0x0004
  140. #define LVL3 0x0008
  141. #define LVL4 0x0010
  142. #define LVL5 0x0020
  143. #define LVL6 0x0040
  144. #define LVL7 0x0080
  145. #define MULTIVERSE_INTI_INT 0x0100
  146. #define MULTIVERSE_WB_INT 0x0200
  147. #define MULTIVERSE_PCI_INT 0x0400
  148. /* interrupt acknowledge */
  149. #define VME_IACK1 0x04
  150. #define VME_IACK2 0x08
  151. #define VME_IACK3 0x0c
  152. #define VME_IACK4 0x10
  153. #define VME_IACK5 0x14
  154. #define VME_IACK6 0x18
  155. #define VME_IACK7 0x1c
  156. #endif /* __MULTIVERSE_H__ */