ddr-gen3.c 12 KB

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  1. /*
  2. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/fsl_ddr_sdram.h>
  11. #include <asm/processor.h>
  12. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  13. #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  14. #endif
  15. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  16. unsigned int ctrl_num)
  17. {
  18. unsigned int i;
  19. volatile ccsr_ddr_t *ddr;
  20. u32 temp_sdram_cfg;
  21. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  22. volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  23. u32 total_gb_size_per_controller;
  24. unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  25. int csn = -1;
  26. #endif
  27. switch (ctrl_num) {
  28. case 0:
  29. ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  30. break;
  31. case 1:
  32. ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  33. break;
  34. default:
  35. printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  36. return;
  37. }
  38. out_be32(&ddr->eor, regs->ddr_eor);
  39. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  40. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  41. cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  42. cs_ea = regs->cs[i].bnds & 0xfff;
  43. if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  44. csn = i;
  45. csn_bnds_backup = regs->cs[i].bnds;
  46. csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  47. if (cs_ea > 0xeff)
  48. *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  49. else
  50. *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  51. debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  52. "change it to 0x%x\n",
  53. csn, csn_bnds_backup, regs->cs[i].bnds);
  54. break;
  55. }
  56. }
  57. #endif
  58. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  59. if (i == 0) {
  60. out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  61. out_be32(&ddr->cs0_config, regs->cs[i].config);
  62. out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  63. } else if (i == 1) {
  64. out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  65. out_be32(&ddr->cs1_config, regs->cs[i].config);
  66. out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  67. } else if (i == 2) {
  68. out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  69. out_be32(&ddr->cs2_config, regs->cs[i].config);
  70. out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  71. } else if (i == 3) {
  72. out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  73. out_be32(&ddr->cs3_config, regs->cs[i].config);
  74. out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  75. }
  76. }
  77. out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  78. out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  79. out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  80. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  81. out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  82. out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  83. out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  84. out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  85. out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  86. out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  87. out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  88. out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  89. out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
  90. out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  91. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  92. out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  93. out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  94. out_be32(&ddr->init_addr, regs->ddr_init_addr);
  95. out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  96. out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  97. out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  98. out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  99. out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  100. out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
  101. out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
  102. out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
  103. out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
  104. out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
  105. out_be32(&ddr->err_disable, regs->err_disable);
  106. out_be32(&ddr->err_int_en, regs->err_int_en);
  107. for (i = 0; i < 32; i++)
  108. out_be32(&ddr->debug[i], regs->debug[i]);
  109. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  110. out_be32(&ddr->debug[12], 0x00000015);
  111. out_be32(&ddr->debug[21], 0x24000000);
  112. #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
  113. /* Set, but do not enable the memory */
  114. temp_sdram_cfg = regs->ddr_sdram_cfg;
  115. temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
  116. out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
  117. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
  118. if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
  119. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
  120. out_be32(&ddr->debug[2], 0x00000400);
  121. out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
  122. out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
  123. out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
  124. out_be32(&ddr->mtcr, 0);
  125. out_be32(&ddr->debug[12], 0x00000015);
  126. out_be32(&ddr->debug[21], 0x24000000);
  127. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
  128. out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
  129. asm volatile("sync;isync");
  130. while (!(in_be32(&ddr->debug[1]) & 0x2))
  131. ;
  132. switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
  133. case 0x00000000:
  134. out_be32(&ddr->sdram_md_cntl,
  135. MD_CNTL_MD_EN |
  136. MD_CNTL_CS_SEL_CS0_CS1 |
  137. 0x04000000 |
  138. MD_CNTL_WRCW |
  139. MD_CNTL_MD_VALUE(0x02));
  140. break;
  141. case 0x00100000:
  142. out_be32(&ddr->sdram_md_cntl,
  143. MD_CNTL_MD_EN |
  144. MD_CNTL_CS_SEL_CS0_CS1 |
  145. 0x04000000 |
  146. MD_CNTL_WRCW |
  147. MD_CNTL_MD_VALUE(0x0a));
  148. break;
  149. case 0x00200000:
  150. out_be32(&ddr->sdram_md_cntl,
  151. MD_CNTL_MD_EN |
  152. MD_CNTL_CS_SEL_CS0_CS1 |
  153. 0x04000000 |
  154. MD_CNTL_WRCW |
  155. MD_CNTL_MD_VALUE(0x12));
  156. break;
  157. case 0x00300000:
  158. out_be32(&ddr->sdram_md_cntl,
  159. MD_CNTL_MD_EN |
  160. MD_CNTL_CS_SEL_CS0_CS1 |
  161. 0x04000000 |
  162. MD_CNTL_WRCW |
  163. MD_CNTL_MD_VALUE(0x1a));
  164. break;
  165. default:
  166. out_be32(&ddr->sdram_md_cntl,
  167. MD_CNTL_MD_EN |
  168. MD_CNTL_CS_SEL_CS0_CS1 |
  169. 0x04000000 |
  170. MD_CNTL_WRCW |
  171. MD_CNTL_MD_VALUE(0x02));
  172. printf("Unsupported RC10\n");
  173. break;
  174. }
  175. while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
  176. ;
  177. udelay(6);
  178. out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
  179. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  180. out_be32(&ddr->debug[2], 0x0);
  181. out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  182. out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  183. out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  184. out_be32(&ddr->debug[12], 0x0);
  185. out_be32(&ddr->debug[21], 0x0);
  186. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  187. }
  188. #endif
  189. /*
  190. * For 8572 DDR1 erratum - DDR controller may enter illegal state
  191. * when operatiing in 32-bit bus mode with 4-beat bursts,
  192. * This erratum does not affect DDR3 mode, only for DDR2 mode.
  193. */
  194. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
  195. if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
  196. && in_be32(&ddr->sdram_cfg) & 0x80000) {
  197. /* set DEBUG_1[31] */
  198. setbits_be32(&ddr->debug[0], 1);
  199. }
  200. #endif
  201. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  202. /*
  203. * This is the combined workaround for DDR111 and DDR134
  204. * following the published errata for MPC8572
  205. */
  206. /* 1. Set EEBACR[3] */
  207. setbits_be32(&ecm->eebacr, 0x10000000);
  208. debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
  209. /* 2. Set DINIT in SDRAM_CFG_2*/
  210. setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
  211. debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
  212. in_be32(&ddr->sdram_cfg_2));
  213. /* 3. Set DEBUG_3[21] */
  214. setbits_be32(&ddr->debug[2], 0x400);
  215. debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
  216. #endif /* part 1 of the workaound */
  217. /*
  218. * 500 painful micro-seconds must elapse between
  219. * the DDR clock setup and the DDR config enable.
  220. * DDR2 need 200 us, and DDR3 need 500 us from spec,
  221. * we choose the max, that is 500 us for all of case.
  222. */
  223. udelay(500);
  224. asm volatile("sync;isync");
  225. /* Let the controller go */
  226. temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
  227. out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
  228. asm volatile("sync;isync");
  229. /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
  230. while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
  231. udelay(10000); /* throttle polling rate */
  232. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  233. /* continue this workaround */
  234. /* 4. Clear DEBUG3[21] */
  235. clrbits_be32(&ddr->debug[2], 0x400);
  236. debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
  237. /* DDR134 workaround starts */
  238. /* A: Clear sdram_cfg_2[odt_cfg] */
  239. clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
  240. debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
  241. in_be32(&ddr->sdram_cfg_2));
  242. /* B: Set DEBUG1[15] */
  243. setbits_be32(&ddr->debug[0], 0x10000);
  244. debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
  245. /* C: Set timing_cfg_2[cpo] to 0b11111 */
  246. setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
  247. debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
  248. in_be32(&ddr->timing_cfg_2));
  249. /* D: Set D6 to 0x9f9f9f9f */
  250. out_be32(&ddr->debug[5], 0x9f9f9f9f);
  251. debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
  252. /* E: Set D7 to 0x9f9f9f9f */
  253. out_be32(&ddr->debug[6], 0x9f9f9f9f);
  254. debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
  255. /* F: Set D2[20] */
  256. setbits_be32(&ddr->debug[1], 0x800);
  257. debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
  258. /* G: Poll on D2[20] until cleared */
  259. while (in_be32(&ddr->debug[1]) & 0x800)
  260. udelay(10000); /* throttle polling rate */
  261. /* H: Clear D1[15] */
  262. clrbits_be32(&ddr->debug[0], 0x10000);
  263. debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
  264. /* I: Set sdram_cfg_2[odt_cfg] */
  265. setbits_be32(&ddr->sdram_cfg_2,
  266. regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
  267. debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
  268. /* Continuing with the DDR111 workaround */
  269. /* 5. Set D2[21] */
  270. setbits_be32(&ddr->debug[1], 0x400);
  271. debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
  272. /* 6. Poll D2[21] until its cleared */
  273. while (in_be32(&ddr->debug[1]) & 0x400)
  274. udelay(10000); /* throttle polling rate */
  275. /* 7. Wait for 400ms/GB */
  276. total_gb_size_per_controller = 0;
  277. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  278. if (i == csn) {
  279. total_gb_size_per_controller +=
  280. ((csn_bnds_backup & 0xFFFF) >> 6)
  281. - (csn_bnds_backup >> 22) + 1;
  282. } else {
  283. total_gb_size_per_controller +=
  284. ((regs->cs[i].bnds & 0xFFFF) >> 6)
  285. - (regs->cs[i].bnds >> 22) + 1;
  286. }
  287. }
  288. if (in_be32(&ddr->sdram_cfg) & 0x80000)
  289. total_gb_size_per_controller <<= 1;
  290. debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
  291. udelay(total_gb_size_per_controller * 400000);
  292. /* 8. Set sdram_cfg_2[dinit] if options requires */
  293. setbits_be32(&ddr->sdram_cfg_2,
  294. regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
  295. debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
  296. /* 9. Poll until dinit is cleared */
  297. while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
  298. udelay(10000);
  299. /* 10. Clear EEBACR[3] */
  300. clrbits_be32(&ecm->eebacr, 10000000);
  301. debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
  302. if (csn != -1) {
  303. csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
  304. *csn_bnds_t = csn_bnds_backup;
  305. debug("Change cs%d_bnds back to 0x%08x\n",
  306. csn, regs->cs[csn].bnds);
  307. setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
  308. switch (csn) {
  309. case 0:
  310. out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
  311. break;
  312. case 1:
  313. out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
  314. break;
  315. case 2:
  316. out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
  317. break;
  318. case 3:
  319. out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
  320. break;
  321. }
  322. clrbits_be32(&ddr->sdram_cfg, 0x2);
  323. }
  324. #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
  325. }