usb_ehci_core.c 18 KB

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  1. /*-
  2. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  3. * Copyright (c) 2008, Excito Elektronik i Skåne AB
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2 of
  9. * the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #define DEBUG
  22. #include <common.h>
  23. #include <asm/byteorder.h>
  24. #include <usb.h>
  25. #include <asm/io.h>
  26. #include <malloc.h>
  27. #include "usb_ehci.h"
  28. int rootdev;
  29. struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  30. volatile struct ehci_hcor *hcor;
  31. static uint16_t portreset;
  32. static struct QH qh_list __attribute__((aligned(32)));
  33. static struct descriptor {
  34. struct usb_hub_descriptor hub;
  35. struct usb_device_descriptor device;
  36. struct usb_linux_config_descriptor config;
  37. struct usb_linux_interface_descriptor interface;
  38. struct usb_endpoint_descriptor endpoint;
  39. } __attribute__ ((packed)) descriptor = {
  40. {
  41. 0x8, /* bDescLength */
  42. 0x29, /* bDescriptorType: hub descriptor */
  43. 2, /* bNrPorts -- runtime modified */
  44. 0, /* wHubCharacteristics */
  45. 0xff, /* bPwrOn2PwrGood */
  46. 0, /* bHubCntrCurrent */
  47. {}, /* Device removable */
  48. {} /* at most 7 ports! XXX */
  49. },
  50. {
  51. 0x12, /* bLength */
  52. 1, /* bDescriptorType: UDESC_DEVICE */
  53. 0x0002, /* bcdUSB: v2.0 */
  54. 9, /* bDeviceClass: UDCLASS_HUB */
  55. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  56. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  57. 64, /* bMaxPacketSize: 64 bytes */
  58. 0x0000, /* idVendor */
  59. 0x0000, /* idProduct */
  60. 0x0001, /* bcdDevice */
  61. 1, /* iManufacturer */
  62. 2, /* iProduct */
  63. 0, /* iSerialNumber */
  64. 1 /* bNumConfigurations: 1 */
  65. },
  66. {
  67. 0x9,
  68. 2, /* bDescriptorType: UDESC_CONFIG */
  69. cpu_to_le16(0x19),
  70. 1, /* bNumInterface */
  71. 1, /* bConfigurationValue */
  72. 0, /* iConfiguration */
  73. 0x40, /* bmAttributes: UC_SELF_POWER */
  74. 0 /* bMaxPower */
  75. },
  76. {
  77. 0x9, /* bLength */
  78. 4, /* bDescriptorType: UDESC_INTERFACE */
  79. 0, /* bInterfaceNumber */
  80. 0, /* bAlternateSetting */
  81. 1, /* bNumEndpoints */
  82. 9, /* bInterfaceClass: UICLASS_HUB */
  83. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  84. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  85. 0 /* iInterface */
  86. },
  87. {
  88. 0x7, /* bLength */
  89. 5, /* bDescriptorType: UDESC_ENDPOINT */
  90. 0x81, /* bEndpointAddress:
  91. * UE_DIR_IN | EHCI_INTR_ENDPT
  92. */
  93. 3, /* bmAttributes: UE_INTERRUPT */
  94. 8, 0, /* wMaxPacketSize */
  95. 255 /* bInterval */
  96. },
  97. };
  98. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int msec)
  99. {
  100. uint32_t result;
  101. do {
  102. result = ehci_readl(ptr);
  103. debug("handshake read reg(%x)=%x\n", (uint32_t)ptr, result);
  104. if (result == ~(uint32_t)0)
  105. return -1;
  106. result &= mask;
  107. if (result == done)
  108. return 0;
  109. wait_ms(1);
  110. msec--;
  111. } while (msec > 0);
  112. return -1;
  113. }
  114. static void ehci_free(void *p, size_t sz)
  115. {
  116. }
  117. static int ehci_reset(void)
  118. {
  119. uint32_t cmd;
  120. uint32_t tmp;
  121. uint32_t *reg_ptr;
  122. int ret = 0;
  123. cmd = ehci_readl(&hcor->or_usbcmd);
  124. cmd |= CMD_RESET;
  125. ehci_writel(&hcor->or_usbcmd, cmd);
  126. ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, 250);
  127. if (ret < 0) {
  128. printf("EHCI fail to reset\n");
  129. goto out;
  130. }
  131. #if defined CONFIG_EHCI_IS_TDI
  132. reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
  133. tmp = ehci_readl(reg_ptr);
  134. tmp |= USBMODE_CM_HC;
  135. #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
  136. tmp |= USBMODE_BE;
  137. #endif
  138. ehci_writel(reg_ptr, tmp);
  139. #endif
  140. out:
  141. return ret;
  142. }
  143. static void *ehci_alloc(size_t sz, size_t align)
  144. {
  145. static struct QH qh __attribute__((aligned(32)));
  146. static struct qTD td[3] __attribute__((aligned (32)));
  147. static int ntds;
  148. void *p;
  149. switch (sz) {
  150. case sizeof(struct QH):
  151. p = &qh;
  152. ntds = 0;
  153. break;
  154. case sizeof(struct qTD):
  155. if (ntds == 3) {
  156. debug("out of TDs\n");
  157. return NULL;
  158. }
  159. p = &td[ntds];
  160. ntds++;
  161. break;
  162. default:
  163. debug("unknown allocation size\n");
  164. return NULL;
  165. }
  166. memset(p, sz, 0);
  167. return p;
  168. }
  169. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  170. {
  171. uint32_t addr, delta, next;
  172. int idx;
  173. addr = (uint32_t) buf;
  174. idx = 0;
  175. while (idx < 5) {
  176. td->qt_buffer[idx] = cpu_to_hc32(addr);
  177. next = (addr + 4096) & ~4095;
  178. delta = next - addr;
  179. if (delta >= sz)
  180. break;
  181. sz -= delta;
  182. addr = next;
  183. idx++;
  184. }
  185. if (idx == 5) {
  186. debug("out of buffer pointers (%u bytes left)\n", sz);
  187. return -1;
  188. }
  189. return 0;
  190. }
  191. static int
  192. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  193. int length, struct devrequest *req)
  194. {
  195. struct QH *qh;
  196. struct qTD *td;
  197. volatile struct qTD *vtd;
  198. unsigned long ts;
  199. uint32_t *tdp;
  200. uint32_t endpt, token, usbsts;
  201. uint32_t c, toggle;
  202. uint32_t cmd;
  203. uint32_t sts;
  204. debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  205. buffer, length, req);
  206. if (req != NULL)
  207. debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  208. req->request, req->request,
  209. req->requesttype, req->requesttype,
  210. le16_to_cpu(req->value), le16_to_cpu(req->value),
  211. le16_to_cpu(req->index));
  212. qh = ehci_alloc(sizeof(struct QH), 32);
  213. if (qh == NULL) {
  214. debug("unable to allocate QH\n");
  215. return -1;
  216. }
  217. qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  218. c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
  219. usb_pipeendpoint(pipe) == 0) ? 1 : 0;
  220. endpt = (8 << 28) |
  221. (c << 27) |
  222. (usb_maxpacket(dev, pipe) << 16) |
  223. (0 << 15) |
  224. (1 << 14) |
  225. (usb_pipespeed(pipe) << 12) |
  226. (usb_pipeendpoint(pipe) << 8) |
  227. (0 << 7) | (usb_pipedevice(pipe) << 0);
  228. qh->qh_endpt1 = cpu_to_hc32(endpt);
  229. endpt = (1 << 30) |
  230. (dev->portnr << 23) |
  231. (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
  232. qh->qh_endpt2 = cpu_to_hc32(endpt);
  233. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  234. qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  235. td = NULL;
  236. tdp = &qh->qh_overlay.qt_next;
  237. toggle =
  238. usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  239. if (req != NULL) {
  240. td = ehci_alloc(sizeof(struct qTD), 32);
  241. if (td == NULL) {
  242. debug("unable to allocate SETUP td\n");
  243. goto fail;
  244. }
  245. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  246. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  247. token = (0 << 31) |
  248. (sizeof(*req) << 16) |
  249. (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
  250. td->qt_token = cpu_to_hc32(token);
  251. if (ehci_td_buffer(td, req, sizeof(*req)) != 0) {
  252. debug("unable construct SETUP td\n");
  253. ehci_free(td, sizeof(*td));
  254. goto fail;
  255. }
  256. *tdp = cpu_to_hc32((uint32_t) td);
  257. tdp = &td->qt_next;
  258. toggle = 1;
  259. }
  260. if (length > 0 || req == NULL) {
  261. td = ehci_alloc(sizeof(struct qTD), 32);
  262. if (td == NULL) {
  263. debug("unable to allocate DATA td\n");
  264. goto fail;
  265. }
  266. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  267. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  268. token = (toggle << 31) |
  269. (length << 16) |
  270. ((req == NULL ? 1 : 0) << 15) |
  271. (0 << 12) |
  272. (3 << 10) |
  273. ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
  274. td->qt_token = cpu_to_hc32(token);
  275. if (ehci_td_buffer(td, buffer, length) != 0) {
  276. debug("unable construct DATA td\n");
  277. ehci_free(td, sizeof(*td));
  278. goto fail;
  279. }
  280. *tdp = cpu_to_hc32((uint32_t) td);
  281. tdp = &td->qt_next;
  282. }
  283. if (req != NULL) {
  284. td = ehci_alloc(sizeof(struct qTD), 32);
  285. if (td == NULL) {
  286. debug("unable to allocate ACK td\n");
  287. goto fail;
  288. }
  289. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  290. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  291. token = (toggle << 31) |
  292. (0 << 16) |
  293. (1 << 15) |
  294. (0 << 12) |
  295. (3 << 10) |
  296. ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
  297. td->qt_token = cpu_to_hc32(token);
  298. *tdp = cpu_to_hc32((uint32_t) td);
  299. tdp = &td->qt_next;
  300. }
  301. qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
  302. usbsts = ehci_readl(&hcor->or_usbsts);
  303. ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
  304. /* Enable async. schedule. */
  305. cmd = ehci_readl(&hcor->or_usbcmd);
  306. cmd |= CMD_ASE;
  307. ehci_writel(&hcor->or_usbcmd, cmd);
  308. sts = ehci_readl(&hcor->or_usbsts);
  309. while ((sts & STD_ASS) == 0) {
  310. sts = ehci_readl(&hcor->or_usbsts);
  311. udelay(10);
  312. }
  313. /* Wait for TDs to be processed. */
  314. ts = get_timer(0);
  315. vtd = td;
  316. do {
  317. token = hc32_to_cpu(vtd->qt_token);
  318. if (!(token & 0x80))
  319. break;
  320. } while (get_timer(ts) < CONFIG_SYS_HZ);
  321. /* Disable async schedule. */
  322. cmd = ehci_readl(&hcor->or_usbcmd);
  323. cmd &= ~CMD_ASE;
  324. ehci_writel(&hcor->or_usbcmd, cmd);
  325. sts = ehci_readl(&hcor->or_usbsts);
  326. while ((sts & STD_ASS) != 0) {
  327. sts = ehci_readl(&hcor->or_usbsts);
  328. udelay(10);
  329. }
  330. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  331. token = hc32_to_cpu(qh->qh_overlay.qt_token);
  332. if (!(token & 0x80)) {
  333. debug("TOKEN=%#x\n", token);
  334. switch (token & 0xfc) {
  335. case 0:
  336. toggle = token >> 31;
  337. usb_settoggle(dev, usb_pipeendpoint(pipe),
  338. usb_pipeout(pipe), toggle);
  339. dev->status = 0;
  340. break;
  341. case 0x40:
  342. dev->status = USB_ST_STALLED;
  343. break;
  344. case 0xa0:
  345. case 0x20:
  346. dev->status = USB_ST_BUF_ERR;
  347. break;
  348. case 0x50:
  349. case 0x10:
  350. dev->status = USB_ST_BABBLE_DET;
  351. break;
  352. default:
  353. dev->status = USB_ST_CRC_ERR;
  354. break;
  355. }
  356. dev->act_len = length - ((token >> 16) & 0x7fff);
  357. } else {
  358. dev->act_len = 0;
  359. debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
  360. dev->devnum, ehci_readl(&hcor->or_usbsts),
  361. ehci_readl(&hcor->or_portsc[0]),
  362. ehci_readl(&hcor->or_portsc[1]));
  363. }
  364. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  365. fail:
  366. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  367. while (td != (void *)QT_NEXT_TERMINATE) {
  368. qh->qh_overlay.qt_next = td->qt_next;
  369. ehci_free(td, sizeof(*td));
  370. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  371. }
  372. ehci_free(qh, sizeof(*qh));
  373. return -1;
  374. }
  375. static inline int min3(int a, int b, int c)
  376. {
  377. if (b < a)
  378. a = b;
  379. if (c < a)
  380. a = c;
  381. return a;
  382. }
  383. int
  384. ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
  385. int length, struct devrequest *req)
  386. {
  387. uint8_t tmpbuf[4];
  388. u16 typeReq;
  389. void *srcptr = NULL;
  390. int len, srclen;
  391. uint32_t reg;
  392. srclen = 0;
  393. debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  394. req->request, req->request,
  395. req->requesttype, req->requesttype,
  396. le16_to_cpu(req->value), le16_to_cpu(req->index));
  397. typeReq = req->request << 8 | req->requesttype;
  398. switch (le16_to_cpu(typeReq)) {
  399. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  400. switch (le16_to_cpu(req->value) >> 8) {
  401. case USB_DT_DEVICE:
  402. debug("USB_DT_DEVICE request\n");
  403. srcptr = &descriptor.device;
  404. srclen = 0x12;
  405. break;
  406. case USB_DT_CONFIG:
  407. debug("USB_DT_CONFIG config\n");
  408. srcptr = &descriptor.config;
  409. srclen = 0x19;
  410. break;
  411. case USB_DT_STRING:
  412. debug("USB_DT_STRING config\n");
  413. switch (le16_to_cpu(req->value) & 0xff) {
  414. case 0: /* Language */
  415. srcptr = "\4\3\1\0";
  416. srclen = 4;
  417. break;
  418. case 1: /* Vendor */
  419. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  420. srclen = 14;
  421. break;
  422. case 2: /* Product */
  423. srcptr = "\52\3E\0H\0C\0I\0 "
  424. "\0H\0o\0s\0t\0 "
  425. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  426. srclen = 42;
  427. break;
  428. default:
  429. debug("unknown value DT_STRING %x\n",
  430. le16_to_cpu(req->value));
  431. goto unknown;
  432. }
  433. break;
  434. default:
  435. debug("unknown value %x\n", le16_to_cpu(req->value));
  436. goto unknown;
  437. }
  438. break;
  439. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  440. switch (le16_to_cpu(req->value) >> 8) {
  441. case USB_DT_HUB:
  442. debug("USB_DT_HUB config\n");
  443. srcptr = &descriptor.hub;
  444. srclen = 0x8;
  445. break;
  446. default:
  447. debug("unknown value %x\n", le16_to_cpu(req->value));
  448. goto unknown;
  449. }
  450. break;
  451. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  452. debug("USB_REQ_SET_ADDRESS\n");
  453. rootdev = le16_to_cpu(req->value);
  454. break;
  455. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  456. debug("USB_REQ_SET_CONFIGURATION\n");
  457. /* Nothing to do */
  458. break;
  459. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  460. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  461. tmpbuf[1] = 0;
  462. srcptr = tmpbuf;
  463. srclen = 2;
  464. break;
  465. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  466. memset(tmpbuf, 0, 4);
  467. reg = ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index)
  468. - 1]);
  469. if (reg & EHCI_PS_CS)
  470. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  471. if (reg & EHCI_PS_PE)
  472. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  473. if (reg & EHCI_PS_SUSP)
  474. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  475. if (reg & EHCI_PS_OCA)
  476. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  477. if (reg & EHCI_PS_PR)
  478. tmpbuf[0] |= USB_PORT_STAT_RESET;
  479. if (reg & EHCI_PS_PP)
  480. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  481. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  482. if (reg & EHCI_PS_CSC)
  483. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  484. if (reg & EHCI_PS_PEC)
  485. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  486. if (reg & EHCI_PS_OCC)
  487. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  488. if (portreset & (1 << le16_to_cpu(req->index)))
  489. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  490. srcptr = tmpbuf;
  491. srclen = 4;
  492. break;
  493. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  494. reg = ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index) - 1]);
  495. reg &= ~EHCI_PS_CLEAR;
  496. switch (le16_to_cpu(req->value)) {
  497. case USB_PORT_FEAT_ENABLE:
  498. reg |= EHCI_PS_PE;
  499. break;
  500. case USB_PORT_FEAT_POWER:
  501. reg |= EHCI_PS_PP;
  502. break;
  503. case USB_PORT_FEAT_RESET:
  504. debug("USB FEAT RESET\n");
  505. if (EHCI_PS_IS_LOWSPEED(reg)) {
  506. /* Low speed device, give up ownership. */
  507. reg |= EHCI_PS_PO;
  508. break;
  509. }
  510. /* Start reset sequence. */
  511. reg &= ~EHCI_PS_PE;
  512. reg |= EHCI_PS_PR;
  513. ehci_writel(&hcor->or_portsc[
  514. le16_to_cpu(req->index) - 1], reg);
  515. /* Wait for reset to complete. */
  516. wait_ms(500);
  517. /* Terminate reset sequence. */
  518. reg &= ~EHCI_PS_PR;
  519. /* TODO: is it only fsl chip that requires this
  520. * manual setting of port enable?
  521. */
  522. reg |= EHCI_PS_PE;
  523. ehci_writel(&hcor->or_portsc[
  524. le16_to_cpu(req->index) - 1], reg);
  525. /* Wait for HC to complete reset. */
  526. wait_ms(10);
  527. reg =
  528. ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index)
  529. - 1]);
  530. reg &= ~EHCI_PS_CLEAR;
  531. if ((reg & EHCI_PS_PE) == 0) {
  532. /* Not a high speed device, give up
  533. * ownership. */
  534. reg |= EHCI_PS_PO;
  535. break;
  536. }
  537. portreset |= 1 << le16_to_cpu(req->index);
  538. break;
  539. default:
  540. debug("unknown feature %x\n", le16_to_cpu(req->value));
  541. goto unknown;
  542. }
  543. ehci_writel(&hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
  544. break;
  545. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  546. reg = ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index) - 1]);
  547. reg &= ~EHCI_PS_CLEAR;
  548. switch (le16_to_cpu(req->value)) {
  549. case USB_PORT_FEAT_ENABLE:
  550. reg &= ~EHCI_PS_PE;
  551. break;
  552. case USB_PORT_FEAT_C_CONNECTION:
  553. reg |= EHCI_PS_CSC;
  554. break;
  555. case USB_PORT_FEAT_OVER_CURRENT:
  556. reg |= EHCI_PS_OCC;
  557. break;
  558. case USB_PORT_FEAT_C_RESET:
  559. portreset &= ~(1 << le16_to_cpu(req->index));
  560. break;
  561. default:
  562. debug("unknown feature %x\n", le16_to_cpu(req->value));
  563. goto unknown;
  564. }
  565. ehci_writel(&hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
  566. break;
  567. default:
  568. debug("Unknown request\n");
  569. goto unknown;
  570. }
  571. wait_ms(1);
  572. len = min3(srclen, le16_to_cpu(req->length), length);
  573. if (srcptr != NULL && len > 0)
  574. memcpy(buffer, srcptr, len);
  575. else
  576. debug("Len is 0\n");
  577. dev->act_len = len;
  578. dev->status = 0;
  579. return 0;
  580. unknown:
  581. debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  582. req->requesttype, req->request, le16_to_cpu(req->value),
  583. le16_to_cpu(req->index), le16_to_cpu(req->length));
  584. dev->act_len = 0;
  585. dev->status = USB_ST_STALLED;
  586. return -1;
  587. }
  588. int usb_lowlevel_stop(void)
  589. {
  590. return ehci_hcd_stop();
  591. }
  592. int usb_lowlevel_init(void)
  593. {
  594. uint32_t reg;
  595. uint32_t cmd;
  596. if (ehci_hcd_init() != 0)
  597. return -1;
  598. /* EHCI spec section 4.1 */
  599. if (ehci_reset() != 0)
  600. return -1;
  601. /* Set head of reclaim list */
  602. memset(&qh_list, 0, sizeof(qh_list));
  603. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  604. qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
  605. qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
  606. qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  607. qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  608. qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
  609. /* Set async. queue head pointer. */
  610. ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
  611. reg = ehci_readl(&hccr->cr_hcsparams);
  612. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  613. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  614. if (reg & 0x10000) /* Port Indicators */
  615. descriptor.hub.wHubCharacteristics |= 0x80;
  616. if (reg & 0x10) /* Port Power Control */
  617. descriptor.hub.wHubCharacteristics |= 0x01;
  618. /* Start the host controller. */
  619. cmd = ehci_readl(&hcor->or_usbcmd);
  620. /* Philips, Intel, and maybe others need CMD_RUN before the
  621. * root hub will detect new devices (why?); NEC doesn't */
  622. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  623. cmd |= CMD_RUN;
  624. ehci_writel(&hcor->or_usbcmd, cmd);
  625. /* take control over the ports */
  626. cmd = ehci_readl(&hcor->or_configflag);
  627. cmd |= FLAG_CF;
  628. ehci_writel(&hcor->or_configflag, cmd);
  629. /* unblock posted writes */
  630. cmd = ehci_readl(&hcor->or_usbcmd);
  631. wait_ms(5);
  632. rootdev = 0;
  633. return 0;
  634. }
  635. int
  636. submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  637. int length)
  638. {
  639. if (usb_pipetype(pipe) != PIPE_BULK) {
  640. debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  641. return -1;
  642. }
  643. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  644. }
  645. int
  646. submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  647. int length, struct devrequest *setup)
  648. {
  649. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  650. debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
  651. return -1;
  652. }
  653. if (usb_pipedevice(pipe) == rootdev) {
  654. if (rootdev == 0)
  655. dev->speed = USB_SPEED_HIGH;
  656. return ehci_submit_root(dev, pipe, buffer, length, setup);
  657. }
  658. return ehci_submit_async(dev, pipe, buffer, length, setup);
  659. }
  660. int
  661. submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  662. int length, int interval)
  663. {
  664. debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  665. dev, pipe, buffer, length, interval);
  666. return -1;
  667. }