dma.h 11 KB

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  1. #ifndef DMA_H
  2. #define DMA_H
  3. /*******************************************************
  4. *
  5. * copyright @ Motorola 1999
  6. *
  7. *******************************************************/
  8. #define NUM_DMA_REG 7
  9. #define DMA_MR_REG 0
  10. #define DMA_SR_REG 1
  11. #define DMA_CDAR_REG 2
  12. #define DMA_SAR_REG 3
  13. #define DMA_DAR_REG 4
  14. #define DMA_BCR_REG 5
  15. #define DMA_NDAR_REG 6
  16. typedef enum _dmastatus
  17. {
  18. DMASUCCESS = 0x1000,
  19. DMALMERROR,
  20. DMAPERROR,
  21. DMACHNBUSY,
  22. DMAEOSINT,
  23. DMAEOCAINT,
  24. DMAINVALID,
  25. DMANOEVENT,
  26. } DMAStatus;
  27. typedef enum _location
  28. {
  29. LOCAL = 0, /* local processor accesses on board DMA,
  30. local processor's eumbbar is required */
  31. REMOTE = 1, /* PCI master accesses DMA on I/O board,
  32. I/O processor's pcsrbar is required */
  33. } LOCATION;
  34. typedef enum dma_mr_bit
  35. {
  36. IRQS = 0x00080000,
  37. PDE = 0x00040000,
  38. DAHTS = 0x00030000,
  39. SAHTS = 0x0000c000,
  40. DAHE = 0x00002000,
  41. SAHE = 0x00001000,
  42. PRC = 0x00000c00,
  43. EIE = 0x00000080,
  44. EOTIE = 0x00000040,
  45. DL = 0x00000008,
  46. CTM = 0x00000004,
  47. CC = 0x00000002,
  48. CS = 0x00000001,
  49. } DMA_MR_BIT;
  50. typedef enum dma_sr_bit
  51. {
  52. LME = 0x00000080,
  53. PE = 0x00000010,
  54. CB = 0x00000004,
  55. EOSI = 0x00000002,
  56. EOCAI = 0x00000001,
  57. } DMA_SR_BIT;
  58. /* structure for DMA Mode Register */
  59. typedef struct _dma_mr
  60. {
  61. unsigned int reserved0 : 12;
  62. unsigned int irqs : 1;
  63. unsigned int pde : 1;
  64. unsigned int dahts : 2;
  65. unsigned int sahts : 2;
  66. unsigned int dahe : 1;
  67. unsigned int sahe : 1;
  68. unsigned int prc : 2;
  69. unsigned int reserved1 : 1;
  70. unsigned int eie : 1;
  71. unsigned int eotie : 1;
  72. unsigned int reserved2 : 3;
  73. unsigned int dl : 1;
  74. unsigned int ctm : 1;
  75. /* if chaining mode is enabled, any time, user can modify the
  76. * descriptor and does not need to halt the current DMA transaction.
  77. * Set CC bit, enable DMA to process the modified descriptors
  78. * Hardware will clear this bit each time, DMA starts.
  79. */
  80. unsigned int cc : 1;
  81. /* cs bit has dua role, halt the current DMA transaction and
  82. * (re)start DMA transaction. In chaining mode, if the descriptor
  83. * needs modification, cs bit shall be used not the cc bit.
  84. * Hardware will not set/clear this bit each time DMA transaction
  85. * stops or starts. Software shall do it.
  86. *
  87. * cs bit shall not be used to halt chaining DMA transaction for
  88. * modifying the descriptor. That is the role of CC bit.
  89. */
  90. unsigned int cs : 1;
  91. } DMA_MR;
  92. /* structure for DMA Status register */
  93. typedef struct _dma_sr
  94. {
  95. unsigned int reserved0 : 24;
  96. unsigned int lme : 1;
  97. unsigned int reserved1 : 2;
  98. unsigned int pe : 1;
  99. unsigned int reserved2 : 1;
  100. unsigned int cb : 1;
  101. unsigned int eosi : 1;
  102. unsigned int eocai : 1;
  103. } DMA_SR;
  104. /* structure for DMA current descriptor address register */
  105. typedef struct _dma_cdar
  106. {
  107. unsigned int cda : 27;
  108. unsigned int snen : 1;
  109. unsigned int eosie : 1;
  110. unsigned int ctt : 2;
  111. unsigned int eotd : 1;
  112. } DMA_CDAR;
  113. /* structure for DMA byte count register */
  114. typedef struct _dma_bcr
  115. {
  116. unsigned int reserved : 6;
  117. unsigned int bcr : 26;
  118. } DMA_BCR;
  119. /* structure for DMA Next Descriptor Address register */
  120. typedef struct _dma_ndar
  121. {
  122. unsigned int nda : 27;
  123. unsigned int ndsnen : 1;
  124. unsigned int ndeosie: 1;
  125. unsigned int ndctt : 2;
  126. unsigned int eotd : 1;
  127. } DMA_NDAR;
  128. /* structure for DMA current transaction info */
  129. typedef struct _dma_curr
  130. {
  131. unsigned int src_addr;
  132. unsigned int dest_addr;
  133. unsigned int byte_cnt;
  134. } DMA_CURR;
  135. /************************* Kernel API********************
  136. * Kernel APIs are used to interface with O.S. kernel.
  137. * They are the functions required by O.S. kernel to
  138. * provide I/O service.
  139. ********************************************************/
  140. /**************DMA Device Control Functions ********/
  141. /**
  142. * Note:
  143. *
  144. * In all following functions, the host (KAHLUA) processor has a
  145. * choice of accessing on board local DMA (LOCAL),
  146. * or DMA on a distributed KAHLUA (REMOTE). In either case,
  147. * the caller shall pass the configured embedded utility memory
  148. * block base address relative to the DMA. If LOCAL DMA is used,
  149. * this parameter shall be EUMBBAR, if REMOTE is used, the
  150. * parameter shall be the corresponding PCSRBAR.
  151. **/
  152. /**************************************************************
  153. * function: DMA_Get_Stat
  154. *
  155. * description: return the content of status register of
  156. * the given DMA channel
  157. * if error, return DMAINVALID. Otherwise return
  158. * DMASUCCESS.
  159. *
  160. **************************************************************/
  161. static DMAStatus DMA_Get_Stat( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_SR * );
  162. /**************************************************************
  163. * function: DMA_Get_Mode
  164. *
  165. * description: return the content of mode register of the
  166. * given DMA channel
  167. * if error, return DMAINVALID. Otherwise return DMASUCCESS.
  168. *
  169. **************************************************************/
  170. static DMAStatus DMA_Get_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR * );
  171. /**************************************************************
  172. * function: DMA_Set_Mode
  173. *
  174. * description: Set a new mode to a given DMA channel
  175. * return DMASUCCESS if success, otherwise return DMACHNINVALID
  176. *
  177. * note: It is not a good idea of changing the DMA mode during
  178. * the middle of a transaction.
  179. **************************************************************/
  180. static DMAStatus DMA_Set_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR mode );
  181. /*************************************************************
  182. * function: DMA_ISR
  183. *
  184. * description: DMA interrupt service routine
  185. * return DMAStatus based on the status
  186. *
  187. *************************************************************/
  188. static DMAStatus DMA_ISR( unsigned int eumbbar,
  189. unsigned int channel,
  190. DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ),
  191. DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ),
  192. DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ),
  193. DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus ));
  194. static DMAStatus dma_error_func( unsigned int, unsigned int, DMAStatus );
  195. /********************* DMA I/O function ********************/
  196. /************************************************************
  197. * function: DMA_Start
  198. *
  199. * description: start a given DMA channel transaction
  200. * return DMASUCCESS if success, otherwise return DMACHNINVALID
  201. *
  202. * note: this function will clear DMA_MR(CC) first, then
  203. * set DMA_MR(CC).
  204. ***********************************************************/
  205. static DMAStatus DMA_Start( LOCATION, unsigned int eumbbar,unsigned int channel );
  206. /***********************************************************
  207. * function: DMA_Halt
  208. *
  209. * description: halt the current dma transaction on the specified
  210. * channel.
  211. * return DMASUCCESS if success, otherwise return DMACHNINVALID
  212. *
  213. * note: if the specified DMA channel is idle, nothing happens
  214. *************************************************************/
  215. static DMAStatus DMA_Halt( LOCATION, unsigned int eumbbar,unsigned int channel );
  216. /*************************************************************
  217. * function: DMA_Chn_Cnt
  218. *
  219. * description: set the DMA_MR(CC) bit for a given channel
  220. * that is in chaining mode.
  221. * return DMASUCCESS if successfule, otherwise return DMACHNINVALID
  222. *
  223. * note: if the given channel is not in chaining mode, nothing
  224. * happen.
  225. *
  226. *************************************************************/
  227. static DMAStatus DMA_Chn_Cnt( LOCATION, unsigned int eumbbar,unsigned int channel );
  228. /*********************** App. API ***************************
  229. * App. API are the APIs Kernel provides for the application
  230. * level program
  231. ************************************************************/
  232. /**************************************************************
  233. * function: DMA_Bld_Curr
  234. *
  235. * description: set current src, dest, byte count registers
  236. * according to the desp for a given channel
  237. *
  238. * if the given channel is busy, no change made,
  239. * return DMACHNBUSY.
  240. *
  241. * otherwise return DMASUCCESS.
  242. *
  243. * note:
  244. **************************************************************/
  245. static DMAStatus DMA_Bld_Curr( LOCATION,
  246. unsigned int eumbbar,
  247. unsigned int channel,
  248. DMA_CURR desp );
  249. /**************************************************************
  250. * function: DMA_Poke_Curr
  251. *
  252. * description: poke the current src, dest, byte count registers
  253. * for a given channel.
  254. *
  255. * return DMASUCCESS if no error otherwise return DMACHNERROR
  256. *
  257. * note: Due to the undeterministic parallelism, in chaining
  258. * mode, the value returned by this function shall
  259. * be taken as reference when the query is made rather
  260. * than the absolute snapshot when the value is returned.
  261. **************************************************************/
  262. static DMAStatus DMA_Poke_Curr( LOCATION,
  263. unsigned int eumbbar,
  264. unsigned int channel,
  265. DMA_CURR* desp );
  266. /**************************************************************
  267. * function: DMA_Bld_Desp
  268. *
  269. * description: set current descriptor address register
  270. * according to the desp for a given channel
  271. *
  272. * if the given channel is busy return DMACHNBUSY
  273. * and no change made, otherwise return DMASUCCESS.
  274. *
  275. * note:
  276. **************************************************************/
  277. static DMAStatus DMA_Bld_Desp( LOCATION host,
  278. unsigned int eumbbar,
  279. unsigned int channel,
  280. DMA_CDAR desp );
  281. /**************************************************************
  282. * function: DMA_Poke_Desp
  283. *
  284. * description: poke the current descriptor address register
  285. * for a given channel
  286. *
  287. * return DMASUCCESS if no error otherwise return
  288. * DMAINVALID
  289. *
  290. * note: Due to the undeterministic parallellism of DMA operation,
  291. * the value returned by this function shall be taken as
  292. * the most recently used descriptor when the last time
  293. * DMA starts a chaining mode operation.
  294. **************************************************************/
  295. static DMAStatus DMA_Poke_Desp( LOCATION,
  296. unsigned int eumbbar,
  297. unsigned int channel,
  298. DMA_CDAR *desp );
  299. #endif