cfi_flash.c 33 KB

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  1. /*
  2. * (C) Copyright 2002-2004
  3. * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
  4. *
  5. * Copyright (C) 2003 Arabella Software Ltd.
  6. * Yuli Barcohen <yuli@arabellasw.com>
  7. * Modified to work with AMD flashes
  8. *
  9. * Copyright (C) 2004
  10. * Ed Okerson
  11. * Modified to work with little-endian systems.
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. *
  31. * History
  32. * 01/20/2004 - combined variants of original driver.
  33. * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
  34. * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
  35. * 01/27/2004 - Little endian support Ed Okerson
  36. *
  37. * Tested Architectures
  38. * Port Width Chip Width # of banks Flash Chip Board
  39. * 32 16 1 28F128J3 seranoa/eagle
  40. * 64 16 1 28F128J3 seranoa/falcon
  41. *
  42. */
  43. /* The DEBUG define must be before common to enable debugging */
  44. /* #define DEBUG */
  45. #include <common.h>
  46. #include <asm/processor.h>
  47. #include <linux/byteorder/swab.h>
  48. #ifdef CFG_FLASH_CFI_DRIVER
  49. /*
  50. * This file implements a Common Flash Interface (CFI) driver for U-Boot.
  51. * The width of the port and the width of the chips are determined at initialization.
  52. * These widths are used to calculate the address for access CFI data structures.
  53. * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
  54. *
  55. * References
  56. * JEDEC Standard JESD68 - Common Flash Interface (CFI)
  57. * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
  58. * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
  59. * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
  60. *
  61. * TODO
  62. *
  63. * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
  64. * Table (ALT) to determine if protection is available
  65. *
  66. * Add support for other command sets Use the PRI and ALT to determine command set
  67. * Verify erase and program timeouts.
  68. */
  69. #ifndef CFG_FLASH_BANKS_LIST
  70. #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
  71. #endif
  72. #define FLASH_CMD_CFI 0x98
  73. #define FLASH_CMD_READ_ID 0x90
  74. #define FLASH_CMD_RESET 0xff
  75. #define FLASH_CMD_BLOCK_ERASE 0x20
  76. #define FLASH_CMD_ERASE_CONFIRM 0xD0
  77. #define FLASH_CMD_WRITE 0x40
  78. #define FLASH_CMD_PROTECT 0x60
  79. #define FLASH_CMD_PROTECT_SET 0x01
  80. #define FLASH_CMD_PROTECT_CLEAR 0xD0
  81. #define FLASH_CMD_CLEAR_STATUS 0x50
  82. #define FLASH_CMD_WRITE_TO_BUFFER 0xE8
  83. #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
  84. #define FLASH_STATUS_DONE 0x80
  85. #define FLASH_STATUS_ESS 0x40
  86. #define FLASH_STATUS_ECLBS 0x20
  87. #define FLASH_STATUS_PSLBS 0x10
  88. #define FLASH_STATUS_VPENS 0x08
  89. #define FLASH_STATUS_PSS 0x04
  90. #define FLASH_STATUS_DPS 0x02
  91. #define FLASH_STATUS_R 0x01
  92. #define FLASH_STATUS_PROTECT 0x01
  93. #define AMD_CMD_RESET 0xF0
  94. #define AMD_CMD_WRITE 0xA0
  95. #define AMD_CMD_ERASE_START 0x80
  96. #define AMD_CMD_ERASE_SECTOR 0x30
  97. #define AMD_STATUS_TOGGLE 0x40
  98. #define AMD_STATUS_ERROR 0x20
  99. #define FLASH_OFFSET_CFI 0x55
  100. #define FLASH_OFFSET_CFI_RESP 0x10
  101. #define FLASH_OFFSET_PRIMARY_VENDOR 0x13
  102. #define FLASH_OFFSET_WTOUT 0x1F
  103. #define FLASH_OFFSET_WBTOUT 0x20
  104. #define FLASH_OFFSET_ETOUT 0x21
  105. #define FLASH_OFFSET_CETOUT 0x22
  106. #define FLASH_OFFSET_WMAX_TOUT 0x23
  107. #define FLASH_OFFSET_WBMAX_TOUT 0x24
  108. #define FLASH_OFFSET_EMAX_TOUT 0x25
  109. #define FLASH_OFFSET_CEMAX_TOUT 0x26
  110. #define FLASH_OFFSET_SIZE 0x27
  111. #define FLASH_OFFSET_INTERFACE 0x28
  112. #define FLASH_OFFSET_BUFFER_SIZE 0x2A
  113. #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
  114. #define FLASH_OFFSET_ERASE_REGIONS 0x2D
  115. #define FLASH_OFFSET_PROTECT 0x02
  116. #define FLASH_OFFSET_USER_PROTECTION 0x85
  117. #define FLASH_OFFSET_INTEL_PROTECTION 0x81
  118. #define FLASH_MAN_CFI 0x01000000
  119. #define CFI_CMDSET_NONE 0
  120. #define CFI_CMDSET_INTEL_EXTENDED 1
  121. #define CFI_CMDSET_AMD_STANDARD 2
  122. #define CFI_CMDSET_INTEL_STANDARD 3
  123. #define CFI_CMDSET_AMD_EXTENDED 4
  124. #define CFI_CMDSET_MITSU_STANDARD 256
  125. #define CFI_CMDSET_MITSU_EXTENDED 257
  126. #define CFI_CMDSET_SST 258
  127. typedef union {
  128. unsigned char c;
  129. unsigned short w;
  130. unsigned long l;
  131. unsigned long long ll;
  132. } cfiword_t;
  133. typedef union {
  134. volatile unsigned char *cp;
  135. volatile unsigned short *wp;
  136. volatile unsigned long *lp;
  137. volatile unsigned long long *llp;
  138. } cfiptr_t;
  139. #define NUM_ERASE_REGIONS 4
  140. static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
  141. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  142. /*-----------------------------------------------------------------------
  143. * Functions
  144. */
  145. typedef unsigned long flash_sect_t;
  146. static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
  147. static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
  148. static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  149. static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
  150. static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  151. static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  152. static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  153. static int flash_detect_cfi (flash_info_t * info);
  154. static ulong flash_get_size (ulong base, int banknum);
  155. static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
  156. static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  157. ulong tout, char *prompt);
  158. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  159. static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
  160. #endif
  161. /*-----------------------------------------------------------------------
  162. * create an address based on the offset and the port width
  163. */
  164. inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
  165. {
  166. return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
  167. }
  168. #ifdef DEBUG
  169. /*-----------------------------------------------------------------------
  170. * Debug support
  171. */
  172. void print_longlong (char *str, unsigned long long data)
  173. {
  174. int i;
  175. char *cp;
  176. cp = (unsigned char *) &data;
  177. for (i = 0; i < 8; i++)
  178. sprintf (&str[i * 2], "%2.2x", *cp++);
  179. }
  180. static void flash_printqry (flash_info_t * info, flash_sect_t sect)
  181. {
  182. cfiptr_t cptr;
  183. int x, y;
  184. for (x = 0; x < 0x40; x += 16 / info->portwidth) {
  185. cptr.cp =
  186. flash_make_addr (info, sect,
  187. x + FLASH_OFFSET_CFI_RESP);
  188. debug ("%p : ", cptr.cp);
  189. for (y = 0; y < 16; y++) {
  190. debug ("%2.2x ", cptr.cp[y]);
  191. }
  192. debug (" ");
  193. for (y = 0; y < 16; y++) {
  194. if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
  195. debug ("%c", cptr.cp[y]);
  196. } else {
  197. debug (".");
  198. }
  199. }
  200. debug ("\n");
  201. }
  202. }
  203. #endif
  204. /*-----------------------------------------------------------------------
  205. * read a character at a port width address
  206. */
  207. inline uchar flash_read_uchar (flash_info_t * info, uint offset)
  208. {
  209. uchar *cp;
  210. cp = flash_make_addr (info, 0, offset);
  211. #if defined(__LITTLE_ENDIAN)
  212. return (cp[0]);
  213. #else
  214. return (cp[info->portwidth - 1]);
  215. #endif
  216. }
  217. /*-----------------------------------------------------------------------
  218. * read a short word by swapping for ppc format.
  219. */
  220. ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
  221. {
  222. uchar *addr;
  223. ushort retval;
  224. #ifdef DEBUG
  225. int x;
  226. #endif
  227. addr = flash_make_addr (info, sect, offset);
  228. #ifdef DEBUG
  229. debug ("ushort addr is at %p info->portwidth = %d\n", addr,
  230. info->portwidth);
  231. for (x = 0; x < 2 * info->portwidth; x++) {
  232. debug ("addr[%x] = 0x%x\n", x, addr[x]);
  233. }
  234. #endif
  235. #if defined(__LITTLE_ENDIAN)
  236. retval = ((addr[(info->portwidth)] << 8) | addr[0]);
  237. #else
  238. retval = ((addr[(2 * info->portwidth) - 1] << 8) |
  239. addr[info->portwidth - 1]);
  240. #endif
  241. debug ("retval = 0x%x\n", retval);
  242. return retval;
  243. }
  244. /*-----------------------------------------------------------------------
  245. * read a long word by picking the least significant byte of each maiximum
  246. * port size word. Swap for ppc format.
  247. */
  248. ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
  249. {
  250. uchar *addr;
  251. ulong retval;
  252. #ifdef DEBUG
  253. int x;
  254. #endif
  255. addr = flash_make_addr (info, sect, offset);
  256. #ifdef DEBUG
  257. debug ("long addr is at %p info->portwidth = %d\n", addr,
  258. info->portwidth);
  259. for (x = 0; x < 4 * info->portwidth; x++) {
  260. debug ("addr[%x] = 0x%x\n", x, addr[x]);
  261. }
  262. #endif
  263. #if defined(__LITTLE_ENDIAN)
  264. retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
  265. (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
  266. #else
  267. retval = (addr[(2 * info->portwidth) - 1] << 24) |
  268. (addr[(info->portwidth) - 1] << 16) |
  269. (addr[(4 * info->portwidth) - 1] << 8) |
  270. addr[(3 * info->portwidth) - 1];
  271. #endif
  272. return retval;
  273. }
  274. /*-----------------------------------------------------------------------
  275. */
  276. unsigned long flash_init (void)
  277. {
  278. unsigned long size = 0;
  279. int i;
  280. /* Init: no FLASHes known */
  281. for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
  282. flash_info[i].flash_id = FLASH_UNKNOWN;
  283. size += flash_info[i].size = flash_get_size (bank_base[i], i);
  284. if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  285. printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
  286. i, flash_info[i].size, flash_info[i].size << 20);
  287. }
  288. }
  289. /* Monitor protection ON by default */
  290. #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
  291. flash_protect (FLAG_PROTECT_SET,
  292. CFG_MONITOR_BASE,
  293. CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
  294. &flash_info[0]);
  295. #endif
  296. return (size);
  297. }
  298. /*-----------------------------------------------------------------------
  299. */
  300. int flash_erase (flash_info_t * info, int s_first, int s_last)
  301. {
  302. int rcode = 0;
  303. int prot;
  304. flash_sect_t sect;
  305. if (info->flash_id != FLASH_MAN_CFI) {
  306. printf ("Can't erase unknown flash type - aborted\n");
  307. return 1;
  308. }
  309. if ((s_first < 0) || (s_first > s_last)) {
  310. printf ("- no sectors to erase\n");
  311. return 1;
  312. }
  313. prot = 0;
  314. for (sect = s_first; sect <= s_last; ++sect) {
  315. if (info->protect[sect]) {
  316. prot++;
  317. }
  318. }
  319. if (prot) {
  320. printf ("- Warning: %d protected sectors will not be erased!\n", prot);
  321. } else {
  322. printf ("\n");
  323. }
  324. for (sect = s_first; sect <= s_last; sect++) {
  325. if (info->protect[sect] == 0) { /* not protected */
  326. switch (info->vendor) {
  327. case CFI_CMDSET_INTEL_STANDARD:
  328. case CFI_CMDSET_INTEL_EXTENDED:
  329. flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
  330. flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
  331. flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
  332. break;
  333. case CFI_CMDSET_AMD_STANDARD:
  334. case CFI_CMDSET_AMD_EXTENDED:
  335. flash_unlock_seq (info, sect);
  336. flash_write_cmd (info, sect, 0x555, AMD_CMD_ERASE_START);
  337. flash_unlock_seq (info, sect);
  338. flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
  339. break;
  340. default:
  341. debug ("Unkown flash vendor %d\n",
  342. info->vendor);
  343. break;
  344. }
  345. if (flash_full_status_check
  346. (info, sect, info->erase_blk_tout, "erase")) {
  347. rcode = 1;
  348. } else
  349. printf (".");
  350. }
  351. }
  352. printf (" done\n");
  353. return rcode;
  354. }
  355. /*-----------------------------------------------------------------------
  356. */
  357. void flash_print_info (flash_info_t * info)
  358. {
  359. int i;
  360. if (info->flash_id != FLASH_MAN_CFI) {
  361. printf ("missing or unknown FLASH type\n");
  362. return;
  363. }
  364. printf ("CFI conformant FLASH (%d x %d)",
  365. (info->portwidth << 3), (info->chipwidth << 3));
  366. printf (" Size: %ld MB in %d Sectors\n",
  367. info->size >> 20, info->sector_count);
  368. printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
  369. info->erase_blk_tout,
  370. info->write_tout,
  371. info->buffer_write_tout,
  372. info->buffer_size);
  373. printf (" Sector Start Addresses:");
  374. for (i = 0; i < info->sector_count; ++i) {
  375. #ifdef CFG_FLASH_EMPTY_INFO
  376. int k;
  377. int size;
  378. int erased;
  379. volatile unsigned long *flash;
  380. /*
  381. * Check if whole sector is erased
  382. */
  383. if (i != (info->sector_count - 1))
  384. size = info->start[i + 1] - info->start[i];
  385. else
  386. size = info->start[0] + info->size - info->start[i];
  387. erased = 1;
  388. flash = (volatile unsigned long *) info->start[i];
  389. size = size >> 2; /* divide by 4 for longword access */
  390. for (k = 0; k < size; k++) {
  391. if (*flash++ != 0xffffffff) {
  392. erased = 0;
  393. break;
  394. }
  395. }
  396. if ((i % 5) == 0)
  397. printf ("\n");
  398. /* print empty and read-only info */
  399. printf (" %08lX%s%s",
  400. info->start[i],
  401. erased ? " E" : " ",
  402. info->protect[i] ? "RO " : " ");
  403. #else
  404. if ((i % 5) == 0)
  405. printf ("\n ");
  406. printf (" %08lX%s",
  407. info->start[i], info->protect[i] ? " (RO)" : " ");
  408. #endif
  409. }
  410. printf ("\n");
  411. return;
  412. }
  413. /*-----------------------------------------------------------------------
  414. * Copy memory to flash, returns:
  415. * 0 - OK
  416. * 1 - write timeout
  417. * 2 - Flash not erased
  418. */
  419. int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  420. {
  421. ulong wp;
  422. ulong cp;
  423. int aln;
  424. cfiword_t cword;
  425. int i, rc;
  426. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  427. int buffered_size;
  428. #endif
  429. int x8mode = 0;
  430. /* special handling of 16 bit devices in 8 bit mode */
  431. if ((info->interface == FLASH_CFI_X8X16)
  432. && (info->chipwidth == FLASH_CFI_BY8)) {
  433. switch (info->vendor) {
  434. case CFI_CMDSET_INTEL_STANDARD:
  435. case CFI_CMDSET_INTEL_EXTENDED:
  436. x8mode = info->portwidth;
  437. info->portwidth >>= 1; /* XXX - Need to test on x9/x16 in parallel. */
  438. /*info->portwidth = FLASH_CFI_8BIT; */ /* XXX - Need to test on x9/x16 in parallel. */
  439. break;
  440. case CFI_CMDSET_AMD_STANDARD:
  441. case CFI_CMDSET_AMD_EXTENDED:
  442. default:
  443. break;
  444. }
  445. }
  446. /* get lower aligned address */
  447. /* get lower aligned address */
  448. wp = (addr & ~(info->portwidth - 1));
  449. /* handle unaligned start */
  450. if ((aln = addr - wp) != 0) {
  451. cword.l = 0;
  452. cp = wp;
  453. for (i = 0; i < aln; ++i, ++cp)
  454. flash_add_byte (info, &cword, (*(uchar *) cp));
  455. for (; (i < info->portwidth) && (cnt > 0); i++) {
  456. flash_add_byte (info, &cword, *src++);
  457. cnt--;
  458. cp++;
  459. }
  460. for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
  461. flash_add_byte (info, &cword, (*(uchar *) cp));
  462. if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
  463. return rc;
  464. wp = cp;
  465. }
  466. /* handle the aligned part */
  467. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  468. buffered_size = (info->portwidth / info->chipwidth);
  469. buffered_size *= info->buffer_size;
  470. while (cnt >= info->portwidth) {
  471. i = buffered_size > cnt ? cnt : buffered_size;
  472. if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
  473. return rc;
  474. wp += i;
  475. src += i;
  476. cnt -= i;
  477. }
  478. #else
  479. while (cnt >= info->portwidth) {
  480. cword.l = 0;
  481. for (i = 0; i < info->portwidth; i++) {
  482. flash_add_byte (info, &cword, *src++);
  483. }
  484. if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
  485. return rc;
  486. wp += info->portwidth;
  487. cnt -= info->portwidth;
  488. }
  489. #endif /* CFG_FLASH_USE_BUFFER_WRITE */
  490. if (cnt == 0) {
  491. return (0);
  492. }
  493. /*
  494. * handle unaligned tail bytes
  495. */
  496. cword.l = 0;
  497. for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
  498. flash_add_byte (info, &cword, *src++);
  499. --cnt;
  500. }
  501. for (; i < info->portwidth; ++i, ++cp) {
  502. flash_add_byte (info, &cword, (*(uchar *) cp));
  503. }
  504. /* special handling of 16 bit devices in 8 bit mode */
  505. if (x8mode) {
  506. info->portwidth = x8mode;;
  507. }
  508. return flash_write_cfiword (info, wp, cword);
  509. }
  510. /*-----------------------------------------------------------------------
  511. */
  512. #ifdef CFG_FLASH_PROTECTION
  513. int flash_real_protect (flash_info_t * info, long sector, int prot)
  514. {
  515. int retcode = 0;
  516. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  517. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
  518. if (prot)
  519. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
  520. else
  521. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
  522. if ((retcode =
  523. flash_full_status_check (info, sector, info->erase_blk_tout,
  524. prot ? "protect" : "unprotect")) == 0) {
  525. info->protect[sector] = prot;
  526. /* Intel's unprotect unprotects all locking */
  527. if (prot == 0) {
  528. flash_sect_t i;
  529. for (i = 0; i < info->sector_count; i++) {
  530. if (info->protect[i])
  531. flash_real_protect (info, i, 1);
  532. }
  533. }
  534. }
  535. return retcode;
  536. }
  537. /*-----------------------------------------------------------------------
  538. * flash_read_user_serial - read the OneTimeProgramming cells
  539. */
  540. void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
  541. int len)
  542. {
  543. uchar *src;
  544. uchar *dst;
  545. dst = buffer;
  546. src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
  547. flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
  548. memcpy (dst, src + offset, len);
  549. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  550. }
  551. /*
  552. * flash_read_factory_serial - read the device Id from the protection area
  553. */
  554. void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
  555. int len)
  556. {
  557. uchar *src;
  558. src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
  559. flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
  560. memcpy (buffer, src + offset, len);
  561. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  562. }
  563. #endif /* CFG_FLASH_PROTECTION */
  564. /*
  565. * flash_is_busy - check to see if the flash is busy
  566. * This routine checks the status of the chip and returns true if the chip is busy
  567. */
  568. static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
  569. {
  570. int retval;
  571. switch (info->vendor) {
  572. case CFI_CMDSET_INTEL_STANDARD:
  573. case CFI_CMDSET_INTEL_EXTENDED:
  574. retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
  575. break;
  576. case CFI_CMDSET_AMD_STANDARD:
  577. case CFI_CMDSET_AMD_EXTENDED:
  578. retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
  579. break;
  580. default:
  581. retval = 0;
  582. }
  583. debug ("flash_is_busy: %d\n", retval);
  584. return retval;
  585. }
  586. /*-----------------------------------------------------------------------
  587. * wait for XSR.7 to be set. Time out with an error if it does not.
  588. * This routine does not set the flash to read-array mode.
  589. */
  590. static int flash_status_check (flash_info_t * info, flash_sect_t sector,
  591. ulong tout, char *prompt)
  592. {
  593. ulong start;
  594. /* Wait for command completion */
  595. start = get_timer (0);
  596. while (flash_is_busy (info, sector)) {
  597. if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
  598. printf ("Flash %s timeout at address %lx data %lx\n",
  599. prompt, info->start[sector],
  600. flash_read_long (info, sector, 0));
  601. flash_write_cmd (info, sector, 0, info->cmd_reset);
  602. return ERR_TIMOUT;
  603. }
  604. }
  605. return ERR_OK;
  606. }
  607. /*-----------------------------------------------------------------------
  608. * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
  609. * This routine sets the flash to read-array mode.
  610. */
  611. static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  612. ulong tout, char *prompt)
  613. {
  614. int retcode;
  615. retcode = flash_status_check (info, sector, tout, prompt);
  616. switch (info->vendor) {
  617. case CFI_CMDSET_INTEL_EXTENDED:
  618. case CFI_CMDSET_INTEL_STANDARD:
  619. if ((retcode != ERR_OK)
  620. && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
  621. retcode = ERR_INVAL;
  622. printf ("Flash %s error at address %lx\n", prompt,
  623. info->start[sector]);
  624. if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
  625. printf ("Command Sequence Error.\n");
  626. } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
  627. printf ("Block Erase Error.\n");
  628. retcode = ERR_NOT_ERASED;
  629. } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
  630. printf ("Locking Error\n");
  631. }
  632. if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
  633. printf ("Block locked.\n");
  634. retcode = ERR_PROTECTED;
  635. }
  636. if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
  637. printf ("Vpp Low Error.\n");
  638. }
  639. flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
  640. break;
  641. default:
  642. break;
  643. }
  644. return retcode;
  645. }
  646. /*-----------------------------------------------------------------------
  647. */
  648. static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
  649. {
  650. #if defined(__LITTLE_ENDIAN)
  651. unsigned short w;
  652. unsigned int l;
  653. unsigned long long ll;
  654. #endif
  655. switch (info->portwidth) {
  656. case FLASH_CFI_8BIT:
  657. cword->c = c;
  658. break;
  659. case FLASH_CFI_16BIT:
  660. #if defined(__LITTLE_ENDIAN)
  661. w = c;
  662. w <<= 8;
  663. cword->w = (cword->w >> 8) | w;
  664. #else
  665. cword->w = (cword->w << 8) | c;
  666. #endif
  667. break;
  668. case FLASH_CFI_32BIT:
  669. #if defined(__LITTLE_ENDIAN)
  670. l = c;
  671. l <<= 24;
  672. cword->l = (cword->l >> 8) | l;
  673. #else
  674. cword->l = (cword->l << 8) | c;
  675. #endif
  676. break;
  677. case FLASH_CFI_64BIT:
  678. #if defined(__LITTLE_ENDIAN)
  679. ll = c;
  680. ll <<= 56;
  681. cword->ll = (cword->ll >> 8) | ll;
  682. #else
  683. cword->ll = (cword->ll << 8) | c;
  684. #endif
  685. break;
  686. }
  687. }
  688. /*-----------------------------------------------------------------------
  689. * make a proper sized command based on the port and chip widths
  690. */
  691. static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
  692. {
  693. int i;
  694. #if defined(__LITTLE_ENDIAN)
  695. ushort stmpw;
  696. uint stmpi;
  697. #endif
  698. uchar *cp = (uchar *) cmdbuf;
  699. for (i = 0; i < info->portwidth; i++)
  700. *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
  701. #if defined(__LITTLE_ENDIAN)
  702. switch (info->portwidth) {
  703. case FLASH_CFI_8BIT:
  704. break;
  705. case FLASH_CFI_16BIT:
  706. stmpw = *(ushort *) cmdbuf;
  707. *(ushort *) cmdbuf = __swab16 (stmpw);
  708. break;
  709. case FLASH_CFI_32BIT:
  710. stmpi = *(uint *) cmdbuf;
  711. *(uint *) cmdbuf = __swab32 (stmpi);
  712. break;
  713. default:
  714. printf("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n");
  715. break;
  716. }
  717. #endif
  718. }
  719. /*
  720. * Write a proper sized command to the correct address
  721. */
  722. static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  723. {
  724. volatile cfiptr_t addr;
  725. cfiword_t cword;
  726. addr.cp = flash_make_addr (info, sect, offset);
  727. flash_make_cmd (info, cmd, &cword);
  728. switch (info->portwidth) {
  729. case FLASH_CFI_8BIT:
  730. debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
  731. cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  732. *addr.cp = cword.c;
  733. break;
  734. case FLASH_CFI_16BIT:
  735. debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
  736. cmd, cword.w,
  737. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  738. *addr.wp = cword.w;
  739. break;
  740. case FLASH_CFI_32BIT:
  741. debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
  742. cmd, cword.l,
  743. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  744. *addr.lp = cword.l;
  745. break;
  746. case FLASH_CFI_64BIT:
  747. #ifdef DEBUG
  748. {
  749. char str[20];
  750. print_longlong (str, cword.ll);
  751. debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
  752. addr.llp, cmd, str,
  753. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  754. }
  755. #endif
  756. *addr.llp = cword.ll;
  757. break;
  758. }
  759. }
  760. static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
  761. {
  762. flash_write_cmd (info, sect, 0x555, 0xAA);
  763. flash_write_cmd (info, sect, 0x2AA, 0x55);
  764. }
  765. /*-----------------------------------------------------------------------
  766. */
  767. static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  768. {
  769. cfiptr_t cptr;
  770. cfiword_t cword;
  771. int retval;
  772. cptr.cp = flash_make_addr (info, sect, offset);
  773. flash_make_cmd (info, cmd, &cword);
  774. debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
  775. switch (info->portwidth) {
  776. case FLASH_CFI_8BIT:
  777. debug ("is= %x %x\n", cptr.cp[0], cword.c);
  778. retval = (cptr.cp[0] == cword.c);
  779. break;
  780. case FLASH_CFI_16BIT:
  781. debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
  782. retval = (cptr.wp[0] == cword.w);
  783. break;
  784. case FLASH_CFI_32BIT:
  785. debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
  786. retval = (cptr.lp[0] == cword.l);
  787. break;
  788. case FLASH_CFI_64BIT:
  789. #ifdef DEBUG
  790. {
  791. char str1[20];
  792. char str2[20];
  793. print_longlong (str1, cptr.llp[0]);
  794. print_longlong (str2, cword.ll);
  795. debug ("is= %s %s\n", str1, str2);
  796. }
  797. #endif
  798. retval = (cptr.llp[0] == cword.ll);
  799. break;
  800. default:
  801. retval = 0;
  802. break;
  803. }
  804. return retval;
  805. }
  806. /*-----------------------------------------------------------------------
  807. */
  808. static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  809. {
  810. cfiptr_t cptr;
  811. cfiword_t cword;
  812. int retval;
  813. cptr.cp = flash_make_addr (info, sect, offset);
  814. flash_make_cmd (info, cmd, &cword);
  815. switch (info->portwidth) {
  816. case FLASH_CFI_8BIT:
  817. retval = ((cptr.cp[0] & cword.c) == cword.c);
  818. break;
  819. case FLASH_CFI_16BIT:
  820. retval = ((cptr.wp[0] & cword.w) == cword.w);
  821. break;
  822. case FLASH_CFI_32BIT:
  823. retval = ((cptr.lp[0] & cword.l) == cword.l);
  824. break;
  825. case FLASH_CFI_64BIT:
  826. retval = ((cptr.llp[0] & cword.ll) == cword.ll);
  827. break;
  828. default:
  829. retval = 0;
  830. break;
  831. }
  832. return retval;
  833. }
  834. /*-----------------------------------------------------------------------
  835. */
  836. static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  837. {
  838. cfiptr_t cptr;
  839. cfiword_t cword;
  840. int retval;
  841. cptr.cp = flash_make_addr (info, sect, offset);
  842. flash_make_cmd (info, cmd, &cword);
  843. switch (info->portwidth) {
  844. case FLASH_CFI_8BIT:
  845. retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
  846. break;
  847. case FLASH_CFI_16BIT:
  848. retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
  849. break;
  850. case FLASH_CFI_32BIT:
  851. retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
  852. break;
  853. case FLASH_CFI_64BIT:
  854. retval = ((cptr.llp[0] & cword.ll) !=
  855. (cptr.llp[0] & cword.ll));
  856. break;
  857. default:
  858. retval = 0;
  859. break;
  860. }
  861. return retval;
  862. }
  863. /*-----------------------------------------------------------------------
  864. * detect if flash is compatible with the Common Flash Interface (CFI)
  865. * http://www.jedec.org/download/search/jesd68.pdf
  866. *
  867. */
  868. static int flash_detect_cfi (flash_info_t * info)
  869. {
  870. debug ("flash detect cfi\n");
  871. for (info->portwidth = FLASH_CFI_8BIT;
  872. info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
  873. for (info->chipwidth = FLASH_CFI_BY8;
  874. info->chipwidth <= info->portwidth;
  875. info->chipwidth <<= 1) {
  876. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  877. flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
  878. if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
  879. && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
  880. && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
  881. info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
  882. debug ("device interface is %d\n",
  883. info->interface);
  884. debug ("found port %d chip %d ",
  885. info->portwidth, info->chipwidth);
  886. debug ("port %d bits chip %d bits\n",
  887. info->portwidth << CFI_FLASH_SHIFT_WIDTH,
  888. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  889. return 1;
  890. }
  891. }
  892. }
  893. debug ("not found\n");
  894. return 0;
  895. }
  896. /*
  897. * The following code cannot be run from FLASH!
  898. *
  899. */
  900. static ulong flash_get_size (ulong base, int banknum)
  901. {
  902. flash_info_t *info = &flash_info[banknum];
  903. int i, j;
  904. flash_sect_t sect_cnt;
  905. unsigned long sector;
  906. unsigned long tmp;
  907. int size_ratio;
  908. uchar num_erase_regions;
  909. int erase_region_size;
  910. int erase_region_count;
  911. info->start[0] = base;
  912. if (flash_detect_cfi (info)) {
  913. info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
  914. #ifdef DEBUG
  915. flash_printqry (info, 0);
  916. #endif
  917. switch (info->vendor) {
  918. case CFI_CMDSET_INTEL_STANDARD:
  919. case CFI_CMDSET_INTEL_EXTENDED:
  920. default:
  921. info->cmd_reset = FLASH_CMD_RESET;
  922. break;
  923. case CFI_CMDSET_AMD_STANDARD:
  924. case CFI_CMDSET_AMD_EXTENDED:
  925. info->cmd_reset = AMD_CMD_RESET;
  926. break;
  927. }
  928. debug ("manufacturer is %d\n", info->vendor);
  929. size_ratio = info->portwidth / info->chipwidth;
  930. /* if the chip is x8/x16 reduce the ratio by half */
  931. if ((info->interface == FLASH_CFI_X8X16)
  932. && (info->chipwidth == FLASH_CFI_BY8)) {
  933. size_ratio >>= 1;
  934. }
  935. num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
  936. debug ("size_ratio %d port %d bits chip %d bits\n",
  937. size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
  938. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  939. debug ("found %d erase regions\n", num_erase_regions);
  940. sect_cnt = 0;
  941. sector = base;
  942. for (i = 0; i < num_erase_regions; i++) {
  943. if (i > NUM_ERASE_REGIONS) {
  944. printf ("%d erase regions found, only %d used\n",
  945. num_erase_regions, NUM_ERASE_REGIONS);
  946. break;
  947. }
  948. tmp = flash_read_long (info, 0,
  949. FLASH_OFFSET_ERASE_REGIONS +
  950. i * 4);
  951. erase_region_size =
  952. (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
  953. tmp >>= 16;
  954. erase_region_count = (tmp & 0xffff) + 1;
  955. printf ("erase_region_count = %d erase_region_size = %d\n",
  956. erase_region_count, erase_region_size);
  957. for (j = 0; j < erase_region_count; j++) {
  958. info->start[sect_cnt] = sector;
  959. sector += (erase_region_size * size_ratio);
  960. info->protect[sect_cnt] =
  961. flash_isset (info, sect_cnt,
  962. FLASH_OFFSET_PROTECT,
  963. FLASH_STATUS_PROTECT);
  964. sect_cnt++;
  965. }
  966. }
  967. info->sector_count = sect_cnt;
  968. /* multiply the size by the number of chips */
  969. info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
  970. info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
  971. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
  972. info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
  973. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
  974. info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
  975. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
  976. info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
  977. info->flash_id = FLASH_MAN_CFI;
  978. }
  979. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  980. return (info->size);
  981. }
  982. /*-----------------------------------------------------------------------
  983. */
  984. static int flash_write_cfiword (flash_info_t * info, ulong dest,
  985. cfiword_t cword)
  986. {
  987. cfiptr_t ctladdr;
  988. cfiptr_t cptr;
  989. int flag;
  990. ctladdr.cp = flash_make_addr (info, 0, 0);
  991. cptr.cp = (uchar *) dest;
  992. /* Check if Flash is (sufficiently) erased */
  993. switch (info->portwidth) {
  994. case FLASH_CFI_8BIT:
  995. flag = ((cptr.cp[0] & cword.c) == cword.c);
  996. break;
  997. case FLASH_CFI_16BIT:
  998. flag = ((cptr.wp[0] & cword.w) == cword.w);
  999. break;
  1000. case FLASH_CFI_32BIT:
  1001. flag = ((cptr.lp[0] & cword.l) == cword.l);
  1002. break;
  1003. case FLASH_CFI_64BIT:
  1004. flag = ((cptr.lp[0] & cword.ll) == cword.ll);
  1005. break;
  1006. default:
  1007. return 2;
  1008. }
  1009. if (!flag)
  1010. return 2;
  1011. /* Disable interrupts which might cause a timeout here */
  1012. flag = disable_interrupts ();
  1013. switch (info->vendor) {
  1014. case CFI_CMDSET_INTEL_EXTENDED:
  1015. case CFI_CMDSET_INTEL_STANDARD:
  1016. flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
  1017. flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
  1018. break;
  1019. case CFI_CMDSET_AMD_EXTENDED:
  1020. case CFI_CMDSET_AMD_STANDARD:
  1021. flash_unlock_seq (info, 0);
  1022. flash_write_cmd (info, 0, 0x555, AMD_CMD_WRITE);
  1023. break;
  1024. }
  1025. switch (info->portwidth) {
  1026. case FLASH_CFI_8BIT:
  1027. cptr.cp[0] = cword.c;
  1028. break;
  1029. case FLASH_CFI_16BIT:
  1030. cptr.wp[0] = cword.w;
  1031. break;
  1032. case FLASH_CFI_32BIT:
  1033. cptr.lp[0] = cword.l;
  1034. break;
  1035. case FLASH_CFI_64BIT:
  1036. cptr.llp[0] = cword.ll;
  1037. break;
  1038. }
  1039. /* re-enable interrupts if necessary */
  1040. if (flag)
  1041. enable_interrupts ();
  1042. return flash_full_status_check (info, 0, info->write_tout, "write");
  1043. }
  1044. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  1045. /* loop through the sectors from the highest address
  1046. * when the passed address is greater or equal to the sector address
  1047. * we have a match
  1048. */
  1049. static flash_sect_t find_sector (flash_info_t * info, ulong addr)
  1050. {
  1051. flash_sect_t sector;
  1052. for (sector = info->sector_count - 1; sector >= 0; sector--) {
  1053. if (addr >= info->start[sector])
  1054. break;
  1055. }
  1056. return sector;
  1057. }
  1058. static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
  1059. int len)
  1060. {
  1061. flash_sect_t sector;
  1062. int cnt;
  1063. int retcode;
  1064. volatile cfiptr_t src;
  1065. volatile cfiptr_t dst;
  1066. src.cp = cp;
  1067. dst.cp = (uchar *) dest;
  1068. sector = find_sector (info, dest);
  1069. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  1070. flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
  1071. if ((retcode =
  1072. flash_status_check (info, sector, info->buffer_write_tout,
  1073. "write to buffer")) == ERR_OK) {
  1074. /* reduce the number of loops by the width of the port */
  1075. switch (info->portwidth) {
  1076. case FLASH_CFI_8BIT:
  1077. cnt = len;
  1078. break;
  1079. case FLASH_CFI_16BIT:
  1080. cnt = len >> 1;
  1081. break;
  1082. case FLASH_CFI_32BIT:
  1083. cnt = len >> 2;
  1084. break;
  1085. case FLASH_CFI_64BIT:
  1086. cnt = len >> 3;
  1087. break;
  1088. default:
  1089. return ERR_INVAL;
  1090. break;
  1091. }
  1092. flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
  1093. while (cnt-- > 0) {
  1094. switch (info->portwidth) {
  1095. case FLASH_CFI_8BIT:
  1096. *dst.cp++ = *src.cp++;
  1097. break;
  1098. case FLASH_CFI_16BIT:
  1099. *dst.wp++ = *src.wp++;
  1100. break;
  1101. case FLASH_CFI_32BIT:
  1102. *dst.lp++ = *src.lp++;
  1103. break;
  1104. case FLASH_CFI_64BIT:
  1105. *dst.llp++ = *src.llp++;
  1106. break;
  1107. default:
  1108. return ERR_INVAL;
  1109. break;
  1110. }
  1111. }
  1112. flash_write_cmd (info, sector, 0,
  1113. FLASH_CMD_WRITE_BUFFER_CONFIRM);
  1114. retcode =
  1115. flash_full_status_check (info, sector,
  1116. info->buffer_write_tout,
  1117. "buffer write");
  1118. }
  1119. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  1120. return retcode;
  1121. }
  1122. #endif /* CFG_USE_FLASH_BUFFER_WRITE */
  1123. #endif /* CFG_FLASH_CFI */