csr.h 2.8 KB

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  1. #ifndef __csr_h
  2. #define __csr_h
  3. /*
  4. * (C) Copyright 2000
  5. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  6. * Marius Groeger <mgroeger@sysgo.de>
  7. *
  8. * Control and Status Register definitions for the MBX
  9. *
  10. *--------------------------------------------------------------------
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. /* bits for control register #1 / status register #1 */
  30. #define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */
  31. #define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */
  32. #define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */
  33. #define CSR1_TPEN 0x10 /* TP manually selected */
  34. #define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */
  35. #define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */
  36. #define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */
  37. #define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */
  38. /* bits for control register #2 */
  39. #define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
  40. #define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
  41. #define CR2_BRDFAIL 0x08 /* Board fail */
  42. #define CR2_SWS1 0x04 /* Software Status #2 LED */
  43. #define CR2_SWS2 0x02 /* Software Status #2 LED */
  44. #define CR2_QSPANRST 0x01 /* Reset QSPAN */
  45. /* bits for status register #2 */
  46. #define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
  47. #define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
  48. #define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */
  49. #define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */
  50. #define SR2_RDY 0x02 /* Flash programming status bit */
  51. #define SR2_FT 0x01 /* Reserved for Factory test purposes */
  52. #define MBX_CSR1 (*((uchar *)CFG_CSR_BASE))
  53. #define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1))
  54. #endif /* __csr_h */