start.S 4.1 KB

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  1. /*
  2. * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
  3. * Scott McNutt <smcnutt@psyent.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <config.h>
  24. #include <version.h>
  25. #if !defined(CONFIG_IDENT_STRING)
  26. #define CONFIG_IDENT_STRING ""
  27. #endif
  28. #define STATUS_INIT 0x8600 /* IE=1, IPRI=2 */
  29. /*************************************************************************
  30. * RESTART
  31. ************************************************************************/
  32. .text
  33. .global _start
  34. _start:
  35. bsr 0f
  36. nop
  37. .long _start
  38. /* GERMS -- The "standard-32" configuration GERMS monitor looks
  39. * for the string "Nios" at flash_base + 0xc (actually it only
  40. * tests for 'N', 'i'). You can leave support for this in place
  41. * as it's only a few words.
  42. */
  43. . = _start + 0x000c
  44. .string "Nios"
  45. .align 4
  46. 0:
  47. /*
  48. * Early setup -- set cwp = HI_LIMIT, IPRI = 2, IE = 1 to
  49. * enable underflow exceptions. Disable cache.
  50. * NOTE: %o7 has return addr -- save in %g7 use later.
  51. */
  52. mov %g7, %o7
  53. pfx 2 /* WVALID */
  54. rdctl %g0
  55. lsri %g0, 1
  56. pfx %hi(STATUS_INIT)
  57. or %g0, %lo(STATUS_INIT)
  58. wrctl %g0 /* update status */
  59. nop
  60. /*
  61. * STACK
  62. */
  63. pfx %hi(CFG_INIT_SP)
  64. movi %sp, %lo(CFG_INIT_SP)
  65. pfx %xhi(CFG_INIT_SP)
  66. movhi %sp, %xlo(CFG_INIT_SP)
  67. mov %fp, %sp
  68. pfx %hi(4*16)
  69. subi %sp, %lo(4*16) /* Space for reg window mgmt */
  70. /*
  71. * RELOCATE -- %g7 has return addr from bsr at _start.
  72. */
  73. pfx %hi(__u_boot_cmd_end)
  74. movi %g5, %lo(__u_boot_cmd_end)
  75. pfx %xhi(__u_boot_cmd_end)
  76. movhi %g5, %xlo(__u_boot_cmd_end) /* %g5 <- end address */
  77. lsli %g7, 1 /* mem = retaddr << 1 */
  78. mov %g6, %g7
  79. subi %g6, 4 /* %g6 <- src addr */
  80. ld %g7, [%g7] /* %g7 <- dst addr */
  81. 1: cmp %g7, %g5
  82. skps cc_nz
  83. br 2f
  84. nop /* delay slot */
  85. ld %g0, [%g6]
  86. addi %g6, 4 /* src++ */
  87. st [%g7], %g0
  88. addi %g7, 4 /* dst++ */
  89. br 1b
  90. nop /* delay slot */
  91. 2:
  92. /*
  93. * Jump to relocation address
  94. */
  95. pfx %hi(reloc@h)
  96. movi %g0, %lo(reloc@h)
  97. pfx %xhi(reloc@h)
  98. movhi %g0, %xlo(reloc@h)
  99. jmp %g0
  100. reloc:
  101. /*
  102. * CLEAR BSS
  103. */
  104. pfx %hi(__bss_end)
  105. movi %g5, %lo(__bss_end)
  106. pfx %xhi(__bss_end)
  107. movhi %g5, %xlo(__bss_end) /* %g5 <- end address */
  108. pfx %hi(__bss_start)
  109. movi %g7, %lo(__bss_start)
  110. pfx %xhi(__bss_start)
  111. movhi %g7, %xlo(__bss_start) /* %g7 <- end address */
  112. movi %g0, 0
  113. 3: cmp %g7, %g5
  114. skps cc_nz
  115. br 4f
  116. nop /* delay slot */
  117. st [%g7], %g0
  118. addi %g7, 4 /* (delay slot) dst++ */
  119. br 3b
  120. nop /* delay slot */
  121. 4:
  122. /*
  123. * Call board_init -- never returns
  124. */
  125. pfx %hi(board_init@h)
  126. movi %g1, %lo(board_init@h)
  127. pfx %xhi(board_init@h)
  128. movhi %g1, %xlo(board_init@h)
  129. call %g1
  130. nop /* Delaly slot */
  131. /* NEVER RETURNS */
  132. /*
  133. * dly_clks -- Nios doesn't have a time/clk reference for simple
  134. * delay loops, so we do our best by counting instruction cycles.
  135. * A control register that counts system clock cycles would be
  136. * a handy feature -- hint for Altera ;-)
  137. */
  138. .globl dly_clks
  139. /* Each loop is 4 instructions as delay slot is always
  140. * executed. Each instruction is approximately 4 clocks
  141. * (according to some lame info from Altera). So ...
  142. * ... each loop is about 16 clocks.
  143. */
  144. dly_clks:
  145. lsri %o0, 4 /* cnt/16 */
  146. 8: skprnz %o0
  147. br 9f
  148. subi %o0, 1 /* cnt--, Delay slot */
  149. br 8b
  150. nop
  151. 9: lret
  152. nop /* Delay slot */
  153. .data
  154. .globl version_string
  155. version_string:
  156. .ascii U_BOOT_VERSION
  157. .ascii " (", __DATE__, " - ", __TIME__, ")"
  158. .ascii CONFIG_IDENT_STRING, "\0"