mxc_i2c.c 6.3 KB

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  1. /*
  2. * i2c driver for Freescale mx31
  3. *
  4. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <asm/io.h>
  26. #if defined(CONFIG_HARD_I2C)
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/imx-regs.h>
  29. #define IADR 0x00
  30. #define IFDR 0x04
  31. #define I2CR 0x08
  32. #define I2SR 0x0c
  33. #define I2DR 0x10
  34. #define I2CR_IEN (1 << 7)
  35. #define I2CR_IIEN (1 << 6)
  36. #define I2CR_MSTA (1 << 5)
  37. #define I2CR_MTX (1 << 4)
  38. #define I2CR_TX_NO_AK (1 << 3)
  39. #define I2CR_RSTA (1 << 2)
  40. #define I2SR_ICF (1 << 7)
  41. #define I2SR_IBB (1 << 5)
  42. #define I2SR_IIF (1 << 1)
  43. #define I2SR_RX_NO_AK (1 << 0)
  44. #if defined(CONFIG_SYS_I2C_MX31_PORT1)
  45. #define I2C_BASE 0x43f80000
  46. #define I2C_CLK_OFFSET 26
  47. #elif defined (CONFIG_SYS_I2C_MX31_PORT2)
  48. #define I2C_BASE 0x43f98000
  49. #define I2C_CLK_OFFSET 28
  50. #elif defined (CONFIG_SYS_I2C_MX31_PORT3)
  51. #define I2C_BASE 0x43f84000
  52. #define I2C_CLK_OFFSET 30
  53. #elif defined(CONFIG_SYS_I2C_MX53_PORT1)
  54. #define I2C_BASE I2C1_BASE_ADDR
  55. #elif defined(CONFIG_SYS_I2C_MX53_PORT2)
  56. #define I2C_BASE I2C2_BASE_ADDR
  57. #elif defined(CONFIG_SYS_I2C_MX35_PORT1)
  58. #define I2C_BASE I2C_BASE_ADDR
  59. #else
  60. #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
  61. #endif
  62. #define I2C_MAX_TIMEOUT 10000
  63. #define I2C_MAX_RETRIES 3
  64. static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
  65. 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
  66. 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
  67. static inline void i2c_reset(void)
  68. {
  69. writew(0, I2C_BASE + I2CR); /* Reset module */
  70. writew(0, I2C_BASE + I2SR);
  71. writew(I2CR_IEN, I2C_BASE + I2CR);
  72. }
  73. void i2c_init(int speed, int unused)
  74. {
  75. int freq;
  76. int i;
  77. #if defined(CONFIG_MX31)
  78. struct clock_control_regs *sc_regs =
  79. (struct clock_control_regs *)CCM_BASE;
  80. /* start the required I2C clock */
  81. writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
  82. &sc_regs->cgr0);
  83. #endif
  84. freq = mxc_get_clock(MXC_IPG_PERCLK);
  85. for (i = 0; i < 0x1f; i++)
  86. if (freq / div[i] <= speed)
  87. break;
  88. debug("%s: speed: %d\n", __func__, speed);
  89. writew(i, I2C_BASE + IFDR);
  90. i2c_reset();
  91. }
  92. static int wait_idle(void)
  93. {
  94. int timeout = I2C_MAX_TIMEOUT;
  95. while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) {
  96. writew(0, I2C_BASE + I2SR);
  97. udelay(1);
  98. }
  99. return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB));
  100. }
  101. static int wait_busy(void)
  102. {
  103. int timeout = I2C_MAX_TIMEOUT;
  104. while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
  105. udelay(1);
  106. writew(0, I2C_BASE + I2SR); /* clear interrupt */
  107. return timeout;
  108. }
  109. static int wait_complete(void)
  110. {
  111. int timeout = I2C_MAX_TIMEOUT;
  112. while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) {
  113. writew(0, I2C_BASE + I2SR);
  114. udelay(1);
  115. }
  116. udelay(200);
  117. writew(0, I2C_BASE + I2SR); /* clear interrupt */
  118. return timeout;
  119. }
  120. static int tx_byte(u8 byte)
  121. {
  122. writew(byte, I2C_BASE + I2DR);
  123. if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
  124. return -1;
  125. return 0;
  126. }
  127. static int rx_byte(int last)
  128. {
  129. if (!wait_complete())
  130. return -1;
  131. if (last)
  132. writew(I2CR_IEN, I2C_BASE + I2CR);
  133. return readw(I2C_BASE + I2DR);
  134. }
  135. int i2c_probe(uchar chip)
  136. {
  137. int ret;
  138. writew(0, I2C_BASE + I2CR); /* Reset module */
  139. writew(I2CR_IEN, I2C_BASE + I2CR);
  140. writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
  141. ret = tx_byte(chip << 1);
  142. writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR);
  143. return ret;
  144. }
  145. static int i2c_addr(uchar chip, uint addr, int alen)
  146. {
  147. int i, retry = 0;
  148. for (retry = 0; retry < 3; retry++) {
  149. if (wait_idle())
  150. break;
  151. i2c_reset();
  152. for (i = 0; i < I2C_MAX_TIMEOUT; i++)
  153. udelay(1);
  154. }
  155. if (retry >= I2C_MAX_RETRIES) {
  156. debug("%s:bus is busy(%x)\n",
  157. __func__, readw(I2C_BASE + I2SR));
  158. return -1;
  159. }
  160. writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
  161. if (!wait_busy()) {
  162. debug("%s:trigger start fail(%x)\n",
  163. __func__, readw(I2C_BASE + I2SR));
  164. return -1;
  165. }
  166. if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
  167. debug("%s:chip address cycle fail(%x)\n",
  168. __func__, readw(I2C_BASE + I2SR));
  169. return -1;
  170. }
  171. while (alen--)
  172. if (tx_byte((addr >> (alen * 8)) & 0xff) ||
  173. (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
  174. debug("%s:device address cycle fail(%x)\n",
  175. __func__, readw(I2C_BASE + I2SR));
  176. return -1;
  177. }
  178. return 0;
  179. }
  180. int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
  181. {
  182. int timeout = I2C_MAX_TIMEOUT;
  183. int ret;
  184. debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
  185. __func__, chip, addr, alen, len);
  186. if (i2c_addr(chip, addr, alen)) {
  187. printf("i2c_addr failed\n");
  188. return -1;
  189. }
  190. writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR);
  191. if (tx_byte(chip << 1 | 1))
  192. return -1;
  193. writew(I2CR_IEN | I2CR_MSTA |
  194. ((len == 1) ? I2CR_TX_NO_AK : 0),
  195. I2C_BASE + I2CR);
  196. ret = readw(I2C_BASE + I2DR);
  197. while (len--) {
  198. ret = rx_byte(len == 0);
  199. if (ret < 0)
  200. return -1;
  201. *buf++ = ret;
  202. if (len <= 1)
  203. writew(I2CR_IEN | I2CR_MSTA |
  204. I2CR_TX_NO_AK,
  205. I2C_BASE + I2CR);
  206. }
  207. writew(I2CR_IEN, I2C_BASE + I2CR);
  208. while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
  209. udelay(1);
  210. return 0;
  211. }
  212. int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
  213. {
  214. int timeout = I2C_MAX_TIMEOUT;
  215. debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
  216. __func__, chip, addr, alen, len);
  217. if (i2c_addr(chip, addr, alen))
  218. return -1;
  219. while (len--)
  220. if (tx_byte(*buf++))
  221. return -1;
  222. writew(I2CR_IEN, I2C_BASE + I2CR);
  223. while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
  224. udelay(1);
  225. return 0;
  226. }
  227. #endif /* CONFIG_HARD_I2C */