ehci-hcd.c 22 KB

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  1. /*-
  2. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  3. * Copyright (c) 2008, Excito Elektronik i Skåne AB
  4. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2 of
  11. * the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/byteorder.h>
  25. #include <usb.h>
  26. #include <asm/io.h>
  27. #include <malloc.h>
  28. #include <watchdog.h>
  29. #include "ehci.h"
  30. int rootdev;
  31. struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  32. volatile struct ehci_hcor *hcor;
  33. static uint16_t portreset;
  34. DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
  35. #define ALIGN_END_ADDR(type, ptr, size) \
  36. ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
  37. static struct descriptor {
  38. struct usb_hub_descriptor hub;
  39. struct usb_device_descriptor device;
  40. struct usb_linux_config_descriptor config;
  41. struct usb_linux_interface_descriptor interface;
  42. struct usb_endpoint_descriptor endpoint;
  43. } __attribute__ ((packed)) descriptor = {
  44. {
  45. 0x8, /* bDescLength */
  46. 0x29, /* bDescriptorType: hub descriptor */
  47. 2, /* bNrPorts -- runtime modified */
  48. 0, /* wHubCharacteristics */
  49. 10, /* bPwrOn2PwrGood */
  50. 0, /* bHubCntrCurrent */
  51. {}, /* Device removable */
  52. {} /* at most 7 ports! XXX */
  53. },
  54. {
  55. 0x12, /* bLength */
  56. 1, /* bDescriptorType: UDESC_DEVICE */
  57. cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  58. 9, /* bDeviceClass: UDCLASS_HUB */
  59. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  60. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  61. 64, /* bMaxPacketSize: 64 bytes */
  62. 0x0000, /* idVendor */
  63. 0x0000, /* idProduct */
  64. cpu_to_le16(0x0100), /* bcdDevice */
  65. 1, /* iManufacturer */
  66. 2, /* iProduct */
  67. 0, /* iSerialNumber */
  68. 1 /* bNumConfigurations: 1 */
  69. },
  70. {
  71. 0x9,
  72. 2, /* bDescriptorType: UDESC_CONFIG */
  73. cpu_to_le16(0x19),
  74. 1, /* bNumInterface */
  75. 1, /* bConfigurationValue */
  76. 0, /* iConfiguration */
  77. 0x40, /* bmAttributes: UC_SELF_POWER */
  78. 0 /* bMaxPower */
  79. },
  80. {
  81. 0x9, /* bLength */
  82. 4, /* bDescriptorType: UDESC_INTERFACE */
  83. 0, /* bInterfaceNumber */
  84. 0, /* bAlternateSetting */
  85. 1, /* bNumEndpoints */
  86. 9, /* bInterfaceClass: UICLASS_HUB */
  87. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  88. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  89. 0 /* iInterface */
  90. },
  91. {
  92. 0x7, /* bLength */
  93. 5, /* bDescriptorType: UDESC_ENDPOINT */
  94. 0x81, /* bEndpointAddress:
  95. * UE_DIR_IN | EHCI_INTR_ENDPT
  96. */
  97. 3, /* bmAttributes: UE_INTERRUPT */
  98. 8, /* wMaxPacketSize */
  99. 255 /* bInterval */
  100. },
  101. };
  102. #if defined(CONFIG_EHCI_IS_TDI)
  103. #define ehci_is_TDI() (1)
  104. #else
  105. #define ehci_is_TDI() (0)
  106. #endif
  107. void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
  108. {
  109. mdelay(50);
  110. }
  111. void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
  112. __attribute__((weak, alias("__ehci_powerup_fixup")));
  113. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
  114. {
  115. uint32_t result;
  116. do {
  117. result = ehci_readl(ptr);
  118. udelay(5);
  119. if (result == ~(uint32_t)0)
  120. return -1;
  121. result &= mask;
  122. if (result == done)
  123. return 0;
  124. usec--;
  125. } while (usec > 0);
  126. return -1;
  127. }
  128. static int ehci_reset(void)
  129. {
  130. uint32_t cmd;
  131. uint32_t tmp;
  132. uint32_t *reg_ptr;
  133. int ret = 0;
  134. cmd = ehci_readl(&hcor->or_usbcmd);
  135. cmd = (cmd & ~CMD_RUN) | CMD_RESET;
  136. ehci_writel(&hcor->or_usbcmd, cmd);
  137. ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
  138. if (ret < 0) {
  139. printf("EHCI fail to reset\n");
  140. goto out;
  141. }
  142. if (ehci_is_TDI()) {
  143. reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
  144. tmp = ehci_readl(reg_ptr);
  145. tmp |= USBMODE_CM_HC;
  146. #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
  147. tmp |= USBMODE_BE;
  148. #endif
  149. ehci_writel(reg_ptr, tmp);
  150. }
  151. #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
  152. cmd = ehci_readl(&hcor->or_txfilltuning);
  153. cmd &= ~TXFIFO_THRESH(0x3f);
  154. cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
  155. ehci_writel(&hcor->or_txfilltuning, cmd);
  156. #endif
  157. out:
  158. return ret;
  159. }
  160. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  161. {
  162. uint32_t delta, next;
  163. uint32_t addr = (uint32_t)buf;
  164. int idx;
  165. if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
  166. debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
  167. flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
  168. idx = 0;
  169. while (idx < QT_BUFFER_CNT) {
  170. td->qt_buffer[idx] = cpu_to_hc32(addr);
  171. td->qt_buffer_hi[idx] = 0;
  172. next = (addr + 4096) & ~4095;
  173. delta = next - addr;
  174. if (delta >= sz)
  175. break;
  176. sz -= delta;
  177. addr = next;
  178. idx++;
  179. }
  180. if (idx == QT_BUFFER_CNT) {
  181. printf("out of buffer pointers (%u bytes left)\n", sz);
  182. return -1;
  183. }
  184. return 0;
  185. }
  186. static int
  187. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  188. int length, struct devrequest *req)
  189. {
  190. ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
  191. ALLOC_ALIGN_BUFFER(struct qTD, qtd, 3, USB_DMA_MINALIGN);
  192. int qtd_counter = 0;
  193. volatile struct qTD *vtd;
  194. unsigned long ts;
  195. uint32_t *tdp;
  196. uint32_t endpt, token, usbsts;
  197. uint32_t c, toggle;
  198. uint32_t cmd;
  199. int timeout;
  200. int ret = 0;
  201. debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  202. buffer, length, req);
  203. if (req != NULL)
  204. debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  205. req->request, req->request,
  206. req->requesttype, req->requesttype,
  207. le16_to_cpu(req->value), le16_to_cpu(req->value),
  208. le16_to_cpu(req->index));
  209. memset(qh, 0, sizeof(struct QH));
  210. memset(qtd, 0, 3 * sizeof(*qtd));
  211. toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  212. /*
  213. * Setup QH (3.6 in ehci-r10.pdf)
  214. *
  215. * qh_link ................. 03-00 H
  216. * qh_endpt1 ............... 07-04 H
  217. * qh_endpt2 ............... 0B-08 H
  218. * - qh_curtd
  219. * qh_overlay.qt_next ...... 13-10 H
  220. * - qh_overlay.qt_altnext
  221. */
  222. qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
  223. c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
  224. usb_pipeendpoint(pipe) == 0) ? 1 : 0;
  225. endpt = (8 << 28) |
  226. (c << 27) |
  227. (usb_maxpacket(dev, pipe) << 16) |
  228. (0 << 15) |
  229. (1 << 14) |
  230. (usb_pipespeed(pipe) << 12) |
  231. (usb_pipeendpoint(pipe) << 8) |
  232. (0 << 7) | (usb_pipedevice(pipe) << 0);
  233. qh->qh_endpt1 = cpu_to_hc32(endpt);
  234. endpt = (1 << 30) |
  235. (dev->portnr << 23) |
  236. (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
  237. qh->qh_endpt2 = cpu_to_hc32(endpt);
  238. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  239. tdp = &qh->qh_overlay.qt_next;
  240. if (req != NULL) {
  241. /*
  242. * Setup request qTD (3.5 in ehci-r10.pdf)
  243. *
  244. * qt_next ................ 03-00 H
  245. * qt_altnext ............. 07-04 H
  246. * qt_token ............... 0B-08 H
  247. *
  248. * [ buffer, buffer_hi ] loaded with "req".
  249. */
  250. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  251. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  252. token = (0 << 31) |
  253. (sizeof(*req) << 16) |
  254. (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
  255. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  256. if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req)) != 0) {
  257. printf("unable construct SETUP td\n");
  258. goto fail;
  259. }
  260. /* Update previous qTD! */
  261. *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
  262. tdp = &qtd[qtd_counter++].qt_next;
  263. toggle = 1;
  264. }
  265. if (length > 0 || req == NULL) {
  266. /*
  267. * Setup request qTD (3.5 in ehci-r10.pdf)
  268. *
  269. * qt_next ................ 03-00 H
  270. * qt_altnext ............. 07-04 H
  271. * qt_token ............... 0B-08 H
  272. *
  273. * [ buffer, buffer_hi ] loaded with "buffer".
  274. */
  275. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  276. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  277. token = (toggle << 31) |
  278. (length << 16) |
  279. ((req == NULL ? 1 : 0) << 15) |
  280. (0 << 12) |
  281. (3 << 10) |
  282. ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
  283. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  284. if (ehci_td_buffer(&qtd[qtd_counter], buffer, length) != 0) {
  285. printf("unable construct DATA td\n");
  286. goto fail;
  287. }
  288. /* Update previous qTD! */
  289. *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
  290. tdp = &qtd[qtd_counter++].qt_next;
  291. }
  292. if (req != NULL) {
  293. /*
  294. * Setup request qTD (3.5 in ehci-r10.pdf)
  295. *
  296. * qt_next ................ 03-00 H
  297. * qt_altnext ............. 07-04 H
  298. * qt_token ............... 0B-08 H
  299. */
  300. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  301. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  302. token = (toggle << 31) |
  303. (0 << 16) |
  304. (1 << 15) |
  305. (0 << 12) |
  306. (3 << 10) |
  307. ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
  308. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  309. /* Update previous qTD! */
  310. *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
  311. tdp = &qtd[qtd_counter++].qt_next;
  312. }
  313. qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
  314. /* Flush dcache */
  315. flush_dcache_range((uint32_t)qh_list,
  316. ALIGN_END_ADDR(struct QH, qh_list, 1));
  317. flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
  318. flush_dcache_range((uint32_t)qtd, ALIGN_END_ADDR(struct qTD, qtd, 3));
  319. /* Set async. queue head pointer. */
  320. ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
  321. usbsts = ehci_readl(&hcor->or_usbsts);
  322. ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
  323. /* Enable async. schedule. */
  324. cmd = ehci_readl(&hcor->or_usbcmd);
  325. cmd |= CMD_ASE;
  326. ehci_writel(&hcor->or_usbcmd, cmd);
  327. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
  328. 100 * 1000);
  329. if (ret < 0) {
  330. printf("EHCI fail timeout STD_ASS set\n");
  331. goto fail;
  332. }
  333. /* Wait for TDs to be processed. */
  334. ts = get_timer(0);
  335. vtd = &qtd[qtd_counter - 1];
  336. timeout = USB_TIMEOUT_MS(pipe);
  337. do {
  338. /* Invalidate dcache */
  339. invalidate_dcache_range((uint32_t)qh_list,
  340. ALIGN_END_ADDR(struct QH, qh_list, 1));
  341. invalidate_dcache_range((uint32_t)qh,
  342. ALIGN_END_ADDR(struct QH, qh, 1));
  343. invalidate_dcache_range((uint32_t)qtd,
  344. ALIGN_END_ADDR(struct qTD, qtd, 3));
  345. token = hc32_to_cpu(vtd->qt_token);
  346. if (!(token & 0x80))
  347. break;
  348. WATCHDOG_RESET();
  349. } while (get_timer(ts) < timeout);
  350. /*
  351. * Invalidate the memory area occupied by buffer
  352. * Don't try to fix the buffer alignment, if it isn't properly
  353. * aligned it's upper layer's fault so let invalidate_dcache_range()
  354. * vow about it. But we have to fix the length as it's actual
  355. * transfer length and can be unaligned. This is potentially
  356. * dangerous operation, it's responsibility of the calling
  357. * code to make sure enough space is reserved.
  358. */
  359. invalidate_dcache_range((uint32_t)buffer,
  360. ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
  361. /* Check that the TD processing happened */
  362. if (token & 0x80) {
  363. printf("EHCI timed out on TD - token=%#x\n", token);
  364. }
  365. /* Disable async schedule. */
  366. cmd = ehci_readl(&hcor->or_usbcmd);
  367. cmd &= ~CMD_ASE;
  368. ehci_writel(&hcor->or_usbcmd, cmd);
  369. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
  370. 100 * 1000);
  371. if (ret < 0) {
  372. printf("EHCI fail timeout STD_ASS reset\n");
  373. goto fail;
  374. }
  375. token = hc32_to_cpu(qh->qh_overlay.qt_token);
  376. if (!(token & 0x80)) {
  377. debug("TOKEN=%#x\n", token);
  378. switch (token & 0xfc) {
  379. case 0:
  380. toggle = token >> 31;
  381. usb_settoggle(dev, usb_pipeendpoint(pipe),
  382. usb_pipeout(pipe), toggle);
  383. dev->status = 0;
  384. break;
  385. case 0x40:
  386. dev->status = USB_ST_STALLED;
  387. break;
  388. case 0xa0:
  389. case 0x20:
  390. dev->status = USB_ST_BUF_ERR;
  391. break;
  392. case 0x50:
  393. case 0x10:
  394. dev->status = USB_ST_BABBLE_DET;
  395. break;
  396. default:
  397. dev->status = USB_ST_CRC_ERR;
  398. if ((token & 0x40) == 0x40)
  399. dev->status |= USB_ST_STALLED;
  400. break;
  401. }
  402. dev->act_len = length - ((token >> 16) & 0x7fff);
  403. } else {
  404. dev->act_len = 0;
  405. debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
  406. dev->devnum, ehci_readl(&hcor->or_usbsts),
  407. ehci_readl(&hcor->or_portsc[0]),
  408. ehci_readl(&hcor->or_portsc[1]));
  409. }
  410. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  411. fail:
  412. return -1;
  413. }
  414. static inline int min3(int a, int b, int c)
  415. {
  416. if (b < a)
  417. a = b;
  418. if (c < a)
  419. a = c;
  420. return a;
  421. }
  422. int
  423. ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
  424. int length, struct devrequest *req)
  425. {
  426. uint8_t tmpbuf[4];
  427. u16 typeReq;
  428. void *srcptr = NULL;
  429. int len, srclen;
  430. uint32_t reg;
  431. uint32_t *status_reg;
  432. if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
  433. printf("The request port(%d) is not configured\n",
  434. le16_to_cpu(req->index) - 1);
  435. return -1;
  436. }
  437. status_reg = (uint32_t *)&hcor->or_portsc[
  438. le16_to_cpu(req->index) - 1];
  439. srclen = 0;
  440. debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  441. req->request, req->request,
  442. req->requesttype, req->requesttype,
  443. le16_to_cpu(req->value), le16_to_cpu(req->index));
  444. typeReq = req->request | req->requesttype << 8;
  445. switch (typeReq) {
  446. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  447. switch (le16_to_cpu(req->value) >> 8) {
  448. case USB_DT_DEVICE:
  449. debug("USB_DT_DEVICE request\n");
  450. srcptr = &descriptor.device;
  451. srclen = 0x12;
  452. break;
  453. case USB_DT_CONFIG:
  454. debug("USB_DT_CONFIG config\n");
  455. srcptr = &descriptor.config;
  456. srclen = 0x19;
  457. break;
  458. case USB_DT_STRING:
  459. debug("USB_DT_STRING config\n");
  460. switch (le16_to_cpu(req->value) & 0xff) {
  461. case 0: /* Language */
  462. srcptr = "\4\3\1\0";
  463. srclen = 4;
  464. break;
  465. case 1: /* Vendor */
  466. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  467. srclen = 14;
  468. break;
  469. case 2: /* Product */
  470. srcptr = "\52\3E\0H\0C\0I\0 "
  471. "\0H\0o\0s\0t\0 "
  472. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  473. srclen = 42;
  474. break;
  475. default:
  476. debug("unknown value DT_STRING %x\n",
  477. le16_to_cpu(req->value));
  478. goto unknown;
  479. }
  480. break;
  481. default:
  482. debug("unknown value %x\n", le16_to_cpu(req->value));
  483. goto unknown;
  484. }
  485. break;
  486. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  487. switch (le16_to_cpu(req->value) >> 8) {
  488. case USB_DT_HUB:
  489. debug("USB_DT_HUB config\n");
  490. srcptr = &descriptor.hub;
  491. srclen = 0x8;
  492. break;
  493. default:
  494. debug("unknown value %x\n", le16_to_cpu(req->value));
  495. goto unknown;
  496. }
  497. break;
  498. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  499. debug("USB_REQ_SET_ADDRESS\n");
  500. rootdev = le16_to_cpu(req->value);
  501. break;
  502. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  503. debug("USB_REQ_SET_CONFIGURATION\n");
  504. /* Nothing to do */
  505. break;
  506. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  507. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  508. tmpbuf[1] = 0;
  509. srcptr = tmpbuf;
  510. srclen = 2;
  511. break;
  512. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  513. memset(tmpbuf, 0, 4);
  514. reg = ehci_readl(status_reg);
  515. if (reg & EHCI_PS_CS)
  516. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  517. if (reg & EHCI_PS_PE)
  518. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  519. if (reg & EHCI_PS_SUSP)
  520. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  521. if (reg & EHCI_PS_OCA)
  522. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  523. if (reg & EHCI_PS_PR)
  524. tmpbuf[0] |= USB_PORT_STAT_RESET;
  525. if (reg & EHCI_PS_PP)
  526. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  527. if (ehci_is_TDI()) {
  528. switch ((reg >> 26) & 3) {
  529. case 0:
  530. break;
  531. case 1:
  532. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  533. break;
  534. case 2:
  535. default:
  536. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  537. break;
  538. }
  539. } else {
  540. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  541. }
  542. if (reg & EHCI_PS_CSC)
  543. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  544. if (reg & EHCI_PS_PEC)
  545. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  546. if (reg & EHCI_PS_OCC)
  547. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  548. if (portreset & (1 << le16_to_cpu(req->index)))
  549. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  550. srcptr = tmpbuf;
  551. srclen = 4;
  552. break;
  553. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  554. reg = ehci_readl(status_reg);
  555. reg &= ~EHCI_PS_CLEAR;
  556. switch (le16_to_cpu(req->value)) {
  557. case USB_PORT_FEAT_ENABLE:
  558. reg |= EHCI_PS_PE;
  559. ehci_writel(status_reg, reg);
  560. break;
  561. case USB_PORT_FEAT_POWER:
  562. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
  563. reg |= EHCI_PS_PP;
  564. ehci_writel(status_reg, reg);
  565. }
  566. break;
  567. case USB_PORT_FEAT_RESET:
  568. if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
  569. !ehci_is_TDI() &&
  570. EHCI_PS_IS_LOWSPEED(reg)) {
  571. /* Low speed device, give up ownership. */
  572. debug("port %d low speed --> companion\n",
  573. req->index - 1);
  574. reg |= EHCI_PS_PO;
  575. ehci_writel(status_reg, reg);
  576. break;
  577. } else {
  578. int ret;
  579. reg |= EHCI_PS_PR;
  580. reg &= ~EHCI_PS_PE;
  581. ehci_writel(status_reg, reg);
  582. /*
  583. * caller must wait, then call GetPortStatus
  584. * usb 2.0 specification say 50 ms resets on
  585. * root
  586. */
  587. ehci_powerup_fixup(status_reg, &reg);
  588. ehci_writel(status_reg, reg & ~EHCI_PS_PR);
  589. /*
  590. * A host controller must terminate the reset
  591. * and stabilize the state of the port within
  592. * 2 milliseconds
  593. */
  594. ret = handshake(status_reg, EHCI_PS_PR, 0,
  595. 2 * 1000);
  596. if (!ret)
  597. portreset |=
  598. 1 << le16_to_cpu(req->index);
  599. else
  600. printf("port(%d) reset error\n",
  601. le16_to_cpu(req->index) - 1);
  602. }
  603. break;
  604. default:
  605. debug("unknown feature %x\n", le16_to_cpu(req->value));
  606. goto unknown;
  607. }
  608. /* unblock posted writes */
  609. (void) ehci_readl(&hcor->or_usbcmd);
  610. break;
  611. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  612. reg = ehci_readl(status_reg);
  613. switch (le16_to_cpu(req->value)) {
  614. case USB_PORT_FEAT_ENABLE:
  615. reg &= ~EHCI_PS_PE;
  616. break;
  617. case USB_PORT_FEAT_C_ENABLE:
  618. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
  619. break;
  620. case USB_PORT_FEAT_POWER:
  621. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
  622. reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
  623. case USB_PORT_FEAT_C_CONNECTION:
  624. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
  625. break;
  626. case USB_PORT_FEAT_OVER_CURRENT:
  627. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
  628. break;
  629. case USB_PORT_FEAT_C_RESET:
  630. portreset &= ~(1 << le16_to_cpu(req->index));
  631. break;
  632. default:
  633. debug("unknown feature %x\n", le16_to_cpu(req->value));
  634. goto unknown;
  635. }
  636. ehci_writel(status_reg, reg);
  637. /* unblock posted write */
  638. (void) ehci_readl(&hcor->or_usbcmd);
  639. break;
  640. default:
  641. debug("Unknown request\n");
  642. goto unknown;
  643. }
  644. mdelay(1);
  645. len = min3(srclen, le16_to_cpu(req->length), length);
  646. if (srcptr != NULL && len > 0)
  647. memcpy(buffer, srcptr, len);
  648. else
  649. debug("Len is 0\n");
  650. dev->act_len = len;
  651. dev->status = 0;
  652. return 0;
  653. unknown:
  654. debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  655. req->requesttype, req->request, le16_to_cpu(req->value),
  656. le16_to_cpu(req->index), le16_to_cpu(req->length));
  657. dev->act_len = 0;
  658. dev->status = USB_ST_STALLED;
  659. return -1;
  660. }
  661. int usb_lowlevel_stop(void)
  662. {
  663. return ehci_hcd_stop();
  664. }
  665. int usb_lowlevel_init(void)
  666. {
  667. uint32_t reg;
  668. uint32_t cmd;
  669. if (ehci_hcd_init() != 0)
  670. return -1;
  671. /* EHCI spec section 4.1 */
  672. if (ehci_reset() != 0)
  673. return -1;
  674. #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
  675. if (ehci_hcd_init() != 0)
  676. return -1;
  677. #endif
  678. /* Set head of reclaim list */
  679. memset(qh_list, 0, sizeof(*qh_list));
  680. qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
  681. qh_list->qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
  682. qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
  683. qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  684. qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  685. qh_list->qh_overlay.qt_token = cpu_to_hc32(0x40);
  686. reg = ehci_readl(&hccr->cr_hcsparams);
  687. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  688. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  689. /* Port Indicators */
  690. if (HCS_INDICATOR(reg))
  691. descriptor.hub.wHubCharacteristics |= 0x80;
  692. /* Port Power Control */
  693. if (HCS_PPC(reg))
  694. descriptor.hub.wHubCharacteristics |= 0x01;
  695. /* Start the host controller. */
  696. cmd = ehci_readl(&hcor->or_usbcmd);
  697. /*
  698. * Philips, Intel, and maybe others need CMD_RUN before the
  699. * root hub will detect new devices (why?); NEC doesn't
  700. */
  701. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  702. cmd |= CMD_RUN;
  703. ehci_writel(&hcor->or_usbcmd, cmd);
  704. /* take control over the ports */
  705. cmd = ehci_readl(&hcor->or_configflag);
  706. cmd |= FLAG_CF;
  707. ehci_writel(&hcor->or_configflag, cmd);
  708. /* unblock posted write */
  709. cmd = ehci_readl(&hcor->or_usbcmd);
  710. mdelay(5);
  711. reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
  712. printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
  713. rootdev = 0;
  714. return 0;
  715. }
  716. int
  717. submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  718. int length)
  719. {
  720. if (usb_pipetype(pipe) != PIPE_BULK) {
  721. debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  722. return -1;
  723. }
  724. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  725. }
  726. int
  727. submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  728. int length, struct devrequest *setup)
  729. {
  730. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  731. debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
  732. return -1;
  733. }
  734. if (usb_pipedevice(pipe) == rootdev) {
  735. if (rootdev == 0)
  736. dev->speed = USB_SPEED_HIGH;
  737. return ehci_submit_root(dev, pipe, buffer, length, setup);
  738. }
  739. return ehci_submit_async(dev, pipe, buffer, length, setup);
  740. }
  741. int
  742. submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  743. int length, int interval)
  744. {
  745. debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  746. dev, pipe, buffer, length, interval);
  747. /*
  748. * Interrupt transfers requiring several transactions are not supported
  749. * because bInterval is ignored.
  750. */
  751. if (length > usb_maxpacket(dev, pipe)) {
  752. printf("%s: Interrupt transfers requiring several transactions "
  753. "are not supported.\n", __func__);
  754. return -1;
  755. }
  756. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  757. }