usb_ohci.c 43 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
  3. *
  4. * (C) Copyright 2003
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. *
  25. * Note: Part of this code has been derived from linux
  26. *
  27. */
  28. /*
  29. * IMPORTANT NOTES
  30. * 1 - you MUST define LITTLEENDIAN in the configuration file for the
  31. * board or this driver will NOT work!
  32. * 2 - this driver is intended for use with USB Mass Storage Devices
  33. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  34. */
  35. #include <common.h>
  36. /* #include <pci.h> no PCI on the S3C2400 */
  37. #ifdef CONFIG_USB_OHCI
  38. #include <s3c2400.h>
  39. #include <malloc.h>
  40. #include <usb.h>
  41. #include "usb_ohci.h"
  42. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  43. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  44. /* For initializing controller (mask in an HCFS mode too) */
  45. #define OHCI_CONTROL_INIT \
  46. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  47. #define readl(a) (*((vu_long *)(a)))
  48. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  49. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  50. #undef DEBUG
  51. #ifdef DEBUG
  52. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  53. #else
  54. #define dbg(format, arg...) do {} while(0)
  55. #endif /* DEBUG */
  56. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  57. #undef SHOW_INFO
  58. #ifdef SHOW_INFO
  59. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  60. #else
  61. #define info(format, arg...) do {} while(0)
  62. #endif
  63. #define m16_swap(x) swap_16(x)
  64. #define m32_swap(x) swap_32(x)
  65. /* global ohci_t */
  66. static ohci_t gohci;
  67. /* this must be aligned to a 256 byte boundary */
  68. struct ohci_hcca ghcca[1];
  69. /* a pointer to the aligned storage */
  70. struct ohci_hcca *phcca;
  71. /* this allocates EDs for all possible endpoints */
  72. struct ohci_device ohci_dev;
  73. /* urb_priv */
  74. urb_priv_t urb_priv;
  75. /* RHSC flag */
  76. int got_rhsc;
  77. /* device which was disconnected */
  78. struct usb_device *devgone;
  79. /*-------------------------------------------------------------------------*/
  80. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  81. * The erratum (#4) description is incorrect. AMD's workaround waits
  82. * till some bits (mostly reserved) are clear; ok for all revs.
  83. */
  84. #define OHCI_QUIRK_AMD756 0xabcd
  85. #define read_roothub(hc, register, mask) ({ \
  86. u32 temp = readl (&hc->regs->roothub.register); \
  87. if (hc->flags & OHCI_QUIRK_AMD756) \
  88. while (temp & mask) \
  89. temp = readl (&hc->regs->roothub.register); \
  90. temp; })
  91. static u32 roothub_a (struct ohci *hc)
  92. { return read_roothub (hc, a, 0xfc0fe000); }
  93. static inline u32 roothub_b (struct ohci *hc)
  94. { return readl (&hc->regs->roothub.b); }
  95. static inline u32 roothub_status (struct ohci *hc)
  96. { return readl (&hc->regs->roothub.status); }
  97. static u32 roothub_portstatus (struct ohci *hc, int i)
  98. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  99. /* forward declaration */
  100. static int hc_interrupt (void);
  101. static void
  102. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  103. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  104. /*-------------------------------------------------------------------------*
  105. * URB support functions
  106. *-------------------------------------------------------------------------*/
  107. /* free HCD-private data associated with this URB */
  108. static void urb_free_priv (urb_priv_t * urb)
  109. {
  110. int i;
  111. int last;
  112. struct td * td;
  113. last = urb->length - 1;
  114. if (last >= 0) {
  115. for (i = 0; i <= last; i++) {
  116. td = urb->td[i];
  117. if (td) {
  118. td->usb_dev = NULL;
  119. urb->td[i] = NULL;
  120. }
  121. }
  122. }
  123. }
  124. /*-------------------------------------------------------------------------*/
  125. #ifdef DEBUG
  126. static int sohci_get_current_frame_number (struct usb_device * dev);
  127. /* debug| print the main components of an URB
  128. * small: 0) header + data packets 1) just header */
  129. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  130. int transfer_len, struct devrequest * setup, char * str, int small)
  131. {
  132. urb_priv_t * purb = &urb_priv;
  133. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  134. str,
  135. sohci_get_current_frame_number (dev),
  136. usb_pipedevice (pipe),
  137. usb_pipeendpoint (pipe),
  138. usb_pipeout (pipe)? 'O': 'I',
  139. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  140. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  141. purb->actual_length,
  142. transfer_len, dev->status);
  143. #ifdef OHCI_VERBOSE_DEBUG
  144. if (!small) {
  145. int i, len;
  146. if (usb_pipecontrol (pipe)) {
  147. printf (__FILE__ ": cmd(8):");
  148. for (i = 0; i < 8 ; i++)
  149. printf (" %02x", ((__u8 *) setup) [i]);
  150. printf ("\n");
  151. }
  152. if (transfer_len > 0 && buffer) {
  153. printf (__FILE__ ": data(%d/%d):",
  154. purb->actual_length,
  155. transfer_len);
  156. len = usb_pipeout (pipe)?
  157. transfer_len: purb->actual_length;
  158. for (i = 0; i < 16 && i < len; i++)
  159. printf (" %02x", ((__u8 *) buffer) [i]);
  160. printf ("%s\n", i < len? "...": "");
  161. }
  162. }
  163. #endif
  164. }
  165. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  166. void ep_print_int_eds (ohci_t *ohci, char * str) {
  167. int i, j;
  168. __u32 * ed_p;
  169. for (i= 0; i < 32; i++) {
  170. j = 5;
  171. ed_p = &(ohci->hcca->int_table [i]);
  172. if (*ed_p == 0)
  173. continue;
  174. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  175. while (*ed_p != 0 && j--) {
  176. ed_t *ed = (ed_t *)m32_swap(ed_p);
  177. printf (" ed: %4x;", ed->hwINFO);
  178. ed_p = &ed->hwNextED;
  179. }
  180. printf ("\n");
  181. }
  182. }
  183. static void ohci_dump_intr_mask (char *label, __u32 mask)
  184. {
  185. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  186. label,
  187. mask,
  188. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  189. (mask & OHCI_INTR_OC) ? " OC" : "",
  190. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  191. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  192. (mask & OHCI_INTR_UE) ? " UE" : "",
  193. (mask & OHCI_INTR_RD) ? " RD" : "",
  194. (mask & OHCI_INTR_SF) ? " SF" : "",
  195. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  196. (mask & OHCI_INTR_SO) ? " SO" : ""
  197. );
  198. }
  199. static void maybe_print_eds (char *label, __u32 value)
  200. {
  201. ed_t *edp = (ed_t *)value;
  202. if (value) {
  203. dbg ("%s %08x", label, value);
  204. dbg ("%08x", edp->hwINFO);
  205. dbg ("%08x", edp->hwTailP);
  206. dbg ("%08x", edp->hwHeadP);
  207. dbg ("%08x", edp->hwNextED);
  208. }
  209. }
  210. static char * hcfs2string (int state)
  211. {
  212. switch (state) {
  213. case OHCI_USB_RESET: return "reset";
  214. case OHCI_USB_RESUME: return "resume";
  215. case OHCI_USB_OPER: return "operational";
  216. case OHCI_USB_SUSPEND: return "suspend";
  217. }
  218. return "?";
  219. }
  220. /* dump control and status registers */
  221. static void ohci_dump_status (ohci_t *controller)
  222. {
  223. struct ohci_regs *regs = controller->regs;
  224. __u32 temp;
  225. temp = readl (&regs->revision) & 0xff;
  226. if (temp != 0x10)
  227. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  228. temp = readl (&regs->control);
  229. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  230. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  231. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  232. (temp & OHCI_CTRL_IR) ? " IR" : "",
  233. hcfs2string (temp & OHCI_CTRL_HCFS),
  234. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  235. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  236. (temp & OHCI_CTRL_IE) ? " IE" : "",
  237. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  238. temp & OHCI_CTRL_CBSR
  239. );
  240. temp = readl (&regs->cmdstatus);
  241. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  242. (temp & OHCI_SOC) >> 16,
  243. (temp & OHCI_OCR) ? " OCR" : "",
  244. (temp & OHCI_BLF) ? " BLF" : "",
  245. (temp & OHCI_CLF) ? " CLF" : "",
  246. (temp & OHCI_HCR) ? " HCR" : ""
  247. );
  248. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  249. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  250. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  251. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  252. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  253. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  254. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  255. maybe_print_eds ("donehead", readl (&regs->donehead));
  256. }
  257. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  258. {
  259. __u32 temp, ndp, i;
  260. temp = roothub_a (controller);
  261. ndp = (temp & RH_A_NDP);
  262. if (verbose) {
  263. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  264. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  265. (temp & RH_A_NOCP) ? " NOCP" : "",
  266. (temp & RH_A_OCPM) ? " OCPM" : "",
  267. (temp & RH_A_DT) ? " DT" : "",
  268. (temp & RH_A_NPS) ? " NPS" : "",
  269. (temp & RH_A_PSM) ? " PSM" : "",
  270. ndp
  271. );
  272. temp = roothub_b (controller);
  273. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  274. temp,
  275. (temp & RH_B_PPCM) >> 16,
  276. (temp & RH_B_DR)
  277. );
  278. temp = roothub_status (controller);
  279. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  280. temp,
  281. (temp & RH_HS_CRWE) ? " CRWE" : "",
  282. (temp & RH_HS_OCIC) ? " OCIC" : "",
  283. (temp & RH_HS_LPSC) ? " LPSC" : "",
  284. (temp & RH_HS_DRWE) ? " DRWE" : "",
  285. (temp & RH_HS_OCI) ? " OCI" : "",
  286. (temp & RH_HS_LPS) ? " LPS" : ""
  287. );
  288. }
  289. for (i = 0; i < ndp; i++) {
  290. temp = roothub_portstatus (controller, i);
  291. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  292. i,
  293. temp,
  294. (temp & RH_PS_PRSC) ? " PRSC" : "",
  295. (temp & RH_PS_OCIC) ? " OCIC" : "",
  296. (temp & RH_PS_PSSC) ? " PSSC" : "",
  297. (temp & RH_PS_PESC) ? " PESC" : "",
  298. (temp & RH_PS_CSC) ? " CSC" : "",
  299. (temp & RH_PS_LSDA) ? " LSDA" : "",
  300. (temp & RH_PS_PPS) ? " PPS" : "",
  301. (temp & RH_PS_PRS) ? " PRS" : "",
  302. (temp & RH_PS_POCI) ? " POCI" : "",
  303. (temp & RH_PS_PSS) ? " PSS" : "",
  304. (temp & RH_PS_PES) ? " PES" : "",
  305. (temp & RH_PS_CCS) ? " CCS" : ""
  306. );
  307. }
  308. }
  309. static void ohci_dump (ohci_t *controller, int verbose)
  310. {
  311. dbg ("OHCI controller usb-%s state", controller->slot_name);
  312. /* dumps some of the state we know about */
  313. ohci_dump_status (controller);
  314. if (verbose)
  315. ep_print_int_eds (controller, "hcca");
  316. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  317. ohci_dump_roothub (controller, 1);
  318. }
  319. #endif /* DEBUG */
  320. /*-------------------------------------------------------------------------*
  321. * Interface functions (URB)
  322. *-------------------------------------------------------------------------*/
  323. /* get a transfer request */
  324. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  325. int transfer_len, struct devrequest *setup, int interval)
  326. {
  327. ohci_t *ohci;
  328. ed_t * ed;
  329. urb_priv_t *purb_priv;
  330. int i, size = 0;
  331. ohci = &gohci;
  332. /* when controller's hung, permit only roothub cleanup attempts
  333. * such as powering down ports */
  334. if (ohci->disabled) {
  335. err("sohci_submit_job: EPIPE");
  336. return -1;
  337. }
  338. /* every endpoint has a ed, locate and fill it */
  339. if (!(ed = ep_add_ed (dev, pipe))) {
  340. err("sohci_submit_job: ENOMEM");
  341. return -1;
  342. }
  343. /* for the private part of the URB we need the number of TDs (size) */
  344. switch (usb_pipetype (pipe)) {
  345. case PIPE_BULK: /* one TD for every 4096 Byte */
  346. size = (transfer_len - 1) / 4096 + 1;
  347. break;
  348. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  349. size = (transfer_len == 0)? 2:
  350. (transfer_len - 1) / 4096 + 3;
  351. break;
  352. }
  353. if (size >= (N_URB_TD - 1)) {
  354. err("need %d TDs, only have %d", size, N_URB_TD);
  355. return -1;
  356. }
  357. purb_priv = &urb_priv;
  358. purb_priv->pipe = pipe;
  359. /* fill the private part of the URB */
  360. purb_priv->length = size;
  361. purb_priv->ed = ed;
  362. purb_priv->actual_length = 0;
  363. /* allocate the TDs */
  364. /* note that td[0] was allocated in ep_add_ed */
  365. for (i = 0; i < size; i++) {
  366. purb_priv->td[i] = td_alloc (dev);
  367. if (!purb_priv->td[i]) {
  368. purb_priv->length = i;
  369. urb_free_priv (purb_priv);
  370. err("sohci_submit_job: ENOMEM");
  371. return -1;
  372. }
  373. }
  374. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  375. urb_free_priv (purb_priv);
  376. err("sohci_submit_job: EINVAL");
  377. return -1;
  378. }
  379. /* link the ed into a chain if is not already */
  380. if (ed->state != ED_OPER)
  381. ep_link (ohci, ed);
  382. /* fill the TDs and link it to the ed */
  383. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  384. return 0;
  385. }
  386. /*-------------------------------------------------------------------------*/
  387. #ifdef DEBUG
  388. /* tell us the current USB frame number */
  389. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  390. {
  391. ohci_t *ohci = &gohci;
  392. return m16_swap (ohci->hcca->frame_no);
  393. }
  394. #endif
  395. /*-------------------------------------------------------------------------*
  396. * ED handling functions
  397. *-------------------------------------------------------------------------*/
  398. /* link an ed into one of the HC chains */
  399. static int ep_link (ohci_t *ohci, ed_t *edi)
  400. {
  401. volatile ed_t *ed = edi;
  402. ed->state = ED_OPER;
  403. switch (ed->type) {
  404. case PIPE_CONTROL:
  405. ed->hwNextED = 0;
  406. if (ohci->ed_controltail == NULL) {
  407. writel (ed, &ohci->regs->ed_controlhead);
  408. } else {
  409. ohci->ed_controltail->hwNextED = m32_swap (ed);
  410. }
  411. ed->ed_prev = ohci->ed_controltail;
  412. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  413. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  414. ohci->hc_control |= OHCI_CTRL_CLE;
  415. writel (ohci->hc_control, &ohci->regs->control);
  416. }
  417. ohci->ed_controltail = edi;
  418. break;
  419. case PIPE_BULK:
  420. ed->hwNextED = 0;
  421. if (ohci->ed_bulktail == NULL) {
  422. writel (ed, &ohci->regs->ed_bulkhead);
  423. } else {
  424. ohci->ed_bulktail->hwNextED = m32_swap (ed);
  425. }
  426. ed->ed_prev = ohci->ed_bulktail;
  427. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  428. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  429. ohci->hc_control |= OHCI_CTRL_BLE;
  430. writel (ohci->hc_control, &ohci->regs->control);
  431. }
  432. ohci->ed_bulktail = edi;
  433. break;
  434. }
  435. return 0;
  436. }
  437. /*-------------------------------------------------------------------------*/
  438. /* unlink an ed from one of the HC chains.
  439. * just the link to the ed is unlinked.
  440. * the link from the ed still points to another operational ed or 0
  441. * so the HC can eventually finish the processing of the unlinked ed */
  442. static int ep_unlink (ohci_t *ohci, ed_t *ed)
  443. {
  444. ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
  445. switch (ed->type) {
  446. case PIPE_CONTROL:
  447. if (ed->ed_prev == NULL) {
  448. if (!ed->hwNextED) {
  449. ohci->hc_control &= ~OHCI_CTRL_CLE;
  450. writel (ohci->hc_control, &ohci->regs->control);
  451. }
  452. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  453. } else {
  454. ed->ed_prev->hwNextED = ed->hwNextED;
  455. }
  456. if (ohci->ed_controltail == ed) {
  457. ohci->ed_controltail = ed->ed_prev;
  458. } else {
  459. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  460. }
  461. break;
  462. case PIPE_BULK:
  463. if (ed->ed_prev == NULL) {
  464. if (!ed->hwNextED) {
  465. ohci->hc_control &= ~OHCI_CTRL_BLE;
  466. writel (ohci->hc_control, &ohci->regs->control);
  467. }
  468. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  469. } else {
  470. ed->ed_prev->hwNextED = ed->hwNextED;
  471. }
  472. if (ohci->ed_bulktail == ed) {
  473. ohci->ed_bulktail = ed->ed_prev;
  474. } else {
  475. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  476. }
  477. break;
  478. }
  479. ed->state = ED_UNLINK;
  480. return 0;
  481. }
  482. /*-------------------------------------------------------------------------*/
  483. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  484. * but the USB stack is a little bit stateless so we do it at every transaction
  485. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  486. * in all other cases the state is left unchanged
  487. * the ed info fields are setted anyway even though most of them should not change */
  488. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  489. {
  490. td_t *td;
  491. ed_t *ed_ret;
  492. volatile ed_t *ed;
  493. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  494. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  495. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  496. err("ep_add_ed: pending delete");
  497. /* pending delete request */
  498. return NULL;
  499. }
  500. if (ed->state == ED_NEW) {
  501. ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
  502. /* dummy td; end of td list for ed */
  503. td = td_alloc (usb_dev);
  504. ed->hwTailP = m32_swap (td);
  505. ed->hwHeadP = ed->hwTailP;
  506. ed->state = ED_UNLINK;
  507. ed->type = usb_pipetype (pipe);
  508. ohci_dev.ed_cnt++;
  509. }
  510. ed->hwINFO = m32_swap (usb_pipedevice (pipe)
  511. | usb_pipeendpoint (pipe) << 7
  512. | (usb_pipeisoc (pipe)? 0x8000: 0)
  513. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  514. | usb_pipeslow (pipe) << 13
  515. | usb_maxpacket (usb_dev, pipe) << 16);
  516. return ed_ret;
  517. }
  518. /*-------------------------------------------------------------------------*
  519. * TD handling functions
  520. *-------------------------------------------------------------------------*/
  521. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  522. static void td_fill (ohci_t *ohci, unsigned int info,
  523. void *data, int len,
  524. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  525. {
  526. volatile td_t *td, *td_pt;
  527. #ifdef OHCI_FILL_TRACE
  528. int i;
  529. #endif
  530. if (index > urb_priv->length) {
  531. err("index > length");
  532. return;
  533. }
  534. /* use this td as the next dummy */
  535. td_pt = urb_priv->td [index];
  536. td_pt->hwNextTD = 0;
  537. /* fill the old dummy TD */
  538. td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
  539. td->ed = urb_priv->ed;
  540. td->next_dl_td = NULL;
  541. td->index = index;
  542. td->data = (__u32)data;
  543. #ifdef OHCI_FILL_TRACE
  544. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  545. for (i = 0; i < len; i++)
  546. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  547. printf("\n");
  548. }
  549. #endif
  550. if (!len)
  551. data = 0;
  552. td->hwINFO = m32_swap (info);
  553. td->hwCBP = m32_swap (data);
  554. if (data)
  555. td->hwBE = m32_swap (data + len - 1);
  556. else
  557. td->hwBE = 0;
  558. td->hwNextTD = m32_swap (td_pt);
  559. td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
  560. /* append to queue */
  561. td->ed->hwTailP = td->hwNextTD;
  562. }
  563. /*-------------------------------------------------------------------------*/
  564. /* prepare all TDs of a transfer */
  565. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  566. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  567. {
  568. ohci_t *ohci = &gohci;
  569. int data_len = transfer_len;
  570. void *data;
  571. int cnt = 0;
  572. __u32 info = 0;
  573. unsigned int toggle = 0;
  574. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  575. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  576. toggle = TD_T_TOGGLE;
  577. } else {
  578. toggle = TD_T_DATA0;
  579. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  580. }
  581. urb->td_cnt = 0;
  582. if (data_len)
  583. data = buffer;
  584. else
  585. data = 0;
  586. switch (usb_pipetype (pipe)) {
  587. case PIPE_BULK:
  588. info = usb_pipeout (pipe)?
  589. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  590. while(data_len > 4096) {
  591. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  592. data += 4096; data_len -= 4096; cnt++;
  593. }
  594. info = usb_pipeout (pipe)?
  595. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  596. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  597. cnt++;
  598. if (!ohci->sleeping)
  599. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  600. break;
  601. case PIPE_CONTROL:
  602. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  603. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  604. if (data_len > 0) {
  605. info = usb_pipeout (pipe)?
  606. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  607. /* NOTE: mishandles transfers >8K, some >4K */
  608. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  609. }
  610. info = usb_pipeout (pipe)?
  611. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  612. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  613. if (!ohci->sleeping)
  614. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  615. break;
  616. }
  617. if (urb->length != cnt)
  618. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  619. }
  620. /*-------------------------------------------------------------------------*
  621. * Done List handling functions
  622. *-------------------------------------------------------------------------*/
  623. /* calculate the transfer length and update the urb */
  624. static void dl_transfer_length(td_t * td)
  625. {
  626. __u32 tdINFO, tdBE, tdCBP;
  627. urb_priv_t *lurb_priv = &urb_priv;
  628. tdINFO = m32_swap (td->hwINFO);
  629. tdBE = m32_swap (td->hwBE);
  630. tdCBP = m32_swap (td->hwCBP);
  631. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  632. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  633. if (tdBE != 0) {
  634. if (td->hwCBP == 0)
  635. lurb_priv->actual_length += tdBE - td->data + 1;
  636. else
  637. lurb_priv->actual_length += tdCBP - td->data;
  638. }
  639. }
  640. }
  641. /*-------------------------------------------------------------------------*/
  642. /* replies to the request have to be on a FIFO basis so
  643. * we reverse the reversed done-list */
  644. static td_t * dl_reverse_done_list (ohci_t *ohci)
  645. {
  646. __u32 td_list_hc;
  647. td_t *td_rev = NULL;
  648. td_t *td_list = NULL;
  649. urb_priv_t *lurb_priv = NULL;
  650. td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
  651. ohci->hcca->done_head = 0;
  652. while (td_list_hc) {
  653. td_list = (td_t *)td_list_hc;
  654. if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
  655. lurb_priv = &urb_priv;
  656. dbg(" USB-error/status: %x : %p",
  657. TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
  658. if (td_list->ed->hwHeadP & m32_swap (0x1)) {
  659. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  660. td_list->ed->hwHeadP =
  661. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
  662. (td_list->ed->hwHeadP & m32_swap (0x2));
  663. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  664. } else
  665. td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
  666. }
  667. }
  668. td_list->next_dl_td = td_rev;
  669. td_rev = td_list;
  670. td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
  671. }
  672. return td_list;
  673. }
  674. /*-------------------------------------------------------------------------*/
  675. /* td done list */
  676. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  677. {
  678. td_t *td_list_next = NULL;
  679. ed_t *ed;
  680. int cc = 0;
  681. int stat = 0;
  682. /* urb_t *urb; */
  683. urb_priv_t *lurb_priv;
  684. __u32 tdINFO, edHeadP, edTailP;
  685. while (td_list) {
  686. td_list_next = td_list->next_dl_td;
  687. lurb_priv = &urb_priv;
  688. tdINFO = m32_swap (td_list->hwINFO);
  689. ed = td_list->ed;
  690. dl_transfer_length(td_list);
  691. /* error code of transfer */
  692. cc = TD_CC_GET (tdINFO);
  693. if (cc != 0) {
  694. dbg("ConditionCode %#x", cc);
  695. stat = cc_to_error[cc];
  696. }
  697. if (ed->state != ED_NEW) {
  698. edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
  699. edTailP = m32_swap (ed->hwTailP);
  700. /* unlink eds if they are not busy */
  701. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  702. ep_unlink (ohci, ed);
  703. }
  704. td_list = td_list_next;
  705. }
  706. return stat;
  707. }
  708. /*-------------------------------------------------------------------------*
  709. * Virtual Root Hub
  710. *-------------------------------------------------------------------------*/
  711. /* Device descriptor */
  712. static __u8 root_hub_dev_des[] =
  713. {
  714. 0x12, /* __u8 bLength; */
  715. 0x01, /* __u8 bDescriptorType; Device */
  716. 0x10, /* __u16 bcdUSB; v1.1 */
  717. 0x01,
  718. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  719. 0x00, /* __u8 bDeviceSubClass; */
  720. 0x00, /* __u8 bDeviceProtocol; */
  721. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  722. 0x00, /* __u16 idVendor; */
  723. 0x00,
  724. 0x00, /* __u16 idProduct; */
  725. 0x00,
  726. 0x00, /* __u16 bcdDevice; */
  727. 0x00,
  728. 0x00, /* __u8 iManufacturer; */
  729. 0x01, /* __u8 iProduct; */
  730. 0x00, /* __u8 iSerialNumber; */
  731. 0x01 /* __u8 bNumConfigurations; */
  732. };
  733. /* Configuration descriptor */
  734. static __u8 root_hub_config_des[] =
  735. {
  736. 0x09, /* __u8 bLength; */
  737. 0x02, /* __u8 bDescriptorType; Configuration */
  738. 0x19, /* __u16 wTotalLength; */
  739. 0x00,
  740. 0x01, /* __u8 bNumInterfaces; */
  741. 0x01, /* __u8 bConfigurationValue; */
  742. 0x00, /* __u8 iConfiguration; */
  743. 0x40, /* __u8 bmAttributes;
  744. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  745. 0x00, /* __u8 MaxPower; */
  746. /* interface */
  747. 0x09, /* __u8 if_bLength; */
  748. 0x04, /* __u8 if_bDescriptorType; Interface */
  749. 0x00, /* __u8 if_bInterfaceNumber; */
  750. 0x00, /* __u8 if_bAlternateSetting; */
  751. 0x01, /* __u8 if_bNumEndpoints; */
  752. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  753. 0x00, /* __u8 if_bInterfaceSubClass; */
  754. 0x00, /* __u8 if_bInterfaceProtocol; */
  755. 0x00, /* __u8 if_iInterface; */
  756. /* endpoint */
  757. 0x07, /* __u8 ep_bLength; */
  758. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  759. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  760. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  761. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  762. 0x00,
  763. 0xff /* __u8 ep_bInterval; 255 ms */
  764. };
  765. static unsigned char root_hub_str_index0[] =
  766. {
  767. 0x04, /* __u8 bLength; */
  768. 0x03, /* __u8 bDescriptorType; String-descriptor */
  769. 0x09, /* __u8 lang ID */
  770. 0x04, /* __u8 lang ID */
  771. };
  772. static unsigned char root_hub_str_index1[] =
  773. {
  774. 28, /* __u8 bLength; */
  775. 0x03, /* __u8 bDescriptorType; String-descriptor */
  776. 'O', /* __u8 Unicode */
  777. 0, /* __u8 Unicode */
  778. 'H', /* __u8 Unicode */
  779. 0, /* __u8 Unicode */
  780. 'C', /* __u8 Unicode */
  781. 0, /* __u8 Unicode */
  782. 'I', /* __u8 Unicode */
  783. 0, /* __u8 Unicode */
  784. ' ', /* __u8 Unicode */
  785. 0, /* __u8 Unicode */
  786. 'R', /* __u8 Unicode */
  787. 0, /* __u8 Unicode */
  788. 'o', /* __u8 Unicode */
  789. 0, /* __u8 Unicode */
  790. 'o', /* __u8 Unicode */
  791. 0, /* __u8 Unicode */
  792. 't', /* __u8 Unicode */
  793. 0, /* __u8 Unicode */
  794. ' ', /* __u8 Unicode */
  795. 0, /* __u8 Unicode */
  796. 'H', /* __u8 Unicode */
  797. 0, /* __u8 Unicode */
  798. 'u', /* __u8 Unicode */
  799. 0, /* __u8 Unicode */
  800. 'b', /* __u8 Unicode */
  801. 0, /* __u8 Unicode */
  802. };
  803. /* Hub class-specific descriptor is constructed dynamically */
  804. /*-------------------------------------------------------------------------*/
  805. #define OK(x) len = (x); break
  806. #ifdef DEBUG
  807. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  808. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  809. #else
  810. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  811. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  812. #endif
  813. #define RD_RH_STAT roothub_status(&gohci)
  814. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  815. /* request to virtual root hub */
  816. int rh_check_port_status(ohci_t *controller)
  817. {
  818. __u32 temp, ndp, i;
  819. int res;
  820. res = -1;
  821. temp = roothub_a (controller);
  822. ndp = (temp & RH_A_NDP);
  823. for (i = 0; i < ndp; i++) {
  824. temp = roothub_portstatus (controller, i);
  825. /* check for a device disconnect */
  826. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  827. (RH_PS_PESC | RH_PS_CSC)) &&
  828. ((temp & RH_PS_CCS) == 0)) {
  829. res = i;
  830. break;
  831. }
  832. }
  833. return res;
  834. }
  835. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  836. void *buffer, int transfer_len, struct devrequest *cmd)
  837. {
  838. void * data = buffer;
  839. int leni = transfer_len;
  840. int len = 0;
  841. int stat = 0;
  842. __u32 datab[4];
  843. __u8 *data_buf = (__u8 *)datab;
  844. __u16 bmRType_bReq;
  845. __u16 wValue;
  846. __u16 wIndex;
  847. __u16 wLength;
  848. #ifdef DEBUG
  849. urb_priv.actual_length = 0;
  850. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  851. #else
  852. wait_ms(1);
  853. #endif
  854. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  855. info("Root-Hub submit IRQ: NOT implemented");
  856. return 0;
  857. }
  858. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  859. wValue = m16_swap (cmd->value);
  860. wIndex = m16_swap (cmd->index);
  861. wLength = m16_swap (cmd->length);
  862. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  863. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  864. switch (bmRType_bReq) {
  865. /* Request Destination:
  866. without flags: Device,
  867. RH_INTERFACE: interface,
  868. RH_ENDPOINT: endpoint,
  869. RH_CLASS means HUB here,
  870. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  871. */
  872. case RH_GET_STATUS:
  873. *(__u16 *) data_buf = m16_swap (1); OK (2);
  874. case RH_GET_STATUS | RH_INTERFACE:
  875. *(__u16 *) data_buf = m16_swap (0); OK (2);
  876. case RH_GET_STATUS | RH_ENDPOINT:
  877. *(__u16 *) data_buf = m16_swap (0); OK (2);
  878. case RH_GET_STATUS | RH_CLASS:
  879. *(__u32 *) data_buf = m32_swap (
  880. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  881. OK (4);
  882. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  883. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  884. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  885. switch (wValue) {
  886. case (RH_ENDPOINT_STALL): OK (0);
  887. }
  888. break;
  889. case RH_CLEAR_FEATURE | RH_CLASS:
  890. switch (wValue) {
  891. case RH_C_HUB_LOCAL_POWER:
  892. OK(0);
  893. case (RH_C_HUB_OVER_CURRENT):
  894. WR_RH_STAT(RH_HS_OCIC); OK (0);
  895. }
  896. break;
  897. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  898. switch (wValue) {
  899. case (RH_PORT_ENABLE):
  900. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  901. case (RH_PORT_SUSPEND):
  902. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  903. case (RH_PORT_POWER):
  904. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  905. case (RH_C_PORT_CONNECTION):
  906. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  907. case (RH_C_PORT_ENABLE):
  908. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  909. case (RH_C_PORT_SUSPEND):
  910. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  911. case (RH_C_PORT_OVER_CURRENT):
  912. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  913. case (RH_C_PORT_RESET):
  914. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  915. }
  916. break;
  917. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  918. switch (wValue) {
  919. case (RH_PORT_SUSPEND):
  920. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  921. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  922. if (RD_RH_PORTSTAT & RH_PS_CCS)
  923. WR_RH_PORTSTAT (RH_PS_PRS);
  924. OK (0);
  925. case (RH_PORT_POWER):
  926. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  927. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  928. if (RD_RH_PORTSTAT & RH_PS_CCS)
  929. WR_RH_PORTSTAT (RH_PS_PES );
  930. OK (0);
  931. }
  932. break;
  933. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  934. case RH_GET_DESCRIPTOR:
  935. switch ((wValue & 0xff00) >> 8) {
  936. case (0x01): /* device descriptor */
  937. len = min_t(unsigned int,
  938. leni,
  939. min_t(unsigned int,
  940. sizeof (root_hub_dev_des),
  941. wLength));
  942. data_buf = root_hub_dev_des; OK(len);
  943. case (0x02): /* configuration descriptor */
  944. len = min_t(unsigned int,
  945. leni,
  946. min_t(unsigned int,
  947. sizeof (root_hub_config_des),
  948. wLength));
  949. data_buf = root_hub_config_des; OK(len);
  950. case (0x03): /* string descriptors */
  951. if(wValue==0x0300) {
  952. len = min_t(unsigned int,
  953. leni,
  954. min_t(unsigned int,
  955. sizeof (root_hub_str_index0),
  956. wLength));
  957. data_buf = root_hub_str_index0;
  958. OK(len);
  959. }
  960. if(wValue==0x0301) {
  961. len = min_t(unsigned int,
  962. leni,
  963. min_t(unsigned int,
  964. sizeof (root_hub_str_index1),
  965. wLength));
  966. data_buf = root_hub_str_index1;
  967. OK(len);
  968. }
  969. default:
  970. stat = USB_ST_STALLED;
  971. }
  972. break;
  973. case RH_GET_DESCRIPTOR | RH_CLASS:
  974. {
  975. __u32 temp = roothub_a (&gohci);
  976. data_buf [0] = 9; /* min length; */
  977. data_buf [1] = 0x29;
  978. data_buf [2] = temp & RH_A_NDP;
  979. data_buf [3] = 0;
  980. if (temp & RH_A_PSM) /* per-port power switching? */
  981. data_buf [3] |= 0x1;
  982. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  983. data_buf [3] |= 0x10;
  984. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  985. data_buf [3] |= 0x8;
  986. /* corresponds to data_buf[4-7] */
  987. datab [1] = 0;
  988. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  989. temp = roothub_b (&gohci);
  990. data_buf [7] = temp & RH_B_DR;
  991. if (data_buf [2] < 7) {
  992. data_buf [8] = 0xff;
  993. } else {
  994. data_buf [0] += 2;
  995. data_buf [8] = (temp & RH_B_DR) >> 8;
  996. data_buf [10] = data_buf [9] = 0xff;
  997. }
  998. len = min_t(unsigned int, leni,
  999. min_t(unsigned int, data_buf [0], wLength));
  1000. OK (len);
  1001. }
  1002. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1003. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1004. default:
  1005. dbg ("unsupported root hub command");
  1006. stat = USB_ST_STALLED;
  1007. }
  1008. #ifdef DEBUG
  1009. ohci_dump_roothub (&gohci, 1);
  1010. #else
  1011. wait_ms(1);
  1012. #endif
  1013. len = min_t(int, len, leni);
  1014. if (data != data_buf)
  1015. memcpy (data, data_buf, len);
  1016. dev->act_len = len;
  1017. dev->status = stat;
  1018. #ifdef DEBUG
  1019. if (transfer_len)
  1020. urb_priv.actual_length = transfer_len;
  1021. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1022. #else
  1023. wait_ms(1);
  1024. #endif
  1025. return stat;
  1026. }
  1027. /*-------------------------------------------------------------------------*/
  1028. /* common code for handling submit messages - used for all but root hub */
  1029. /* accesses. */
  1030. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1031. int transfer_len, struct devrequest *setup, int interval)
  1032. {
  1033. int stat = 0;
  1034. int maxsize = usb_maxpacket(dev, pipe);
  1035. int timeout;
  1036. /* device pulled? Shortcut the action. */
  1037. if (devgone == dev) {
  1038. dev->status = USB_ST_CRC_ERR;
  1039. return 0;
  1040. }
  1041. #ifdef DEBUG
  1042. urb_priv.actual_length = 0;
  1043. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1044. #else
  1045. wait_ms(1);
  1046. #endif
  1047. if (!maxsize) {
  1048. err("submit_common_message: pipesize for pipe %lx is zero",
  1049. pipe);
  1050. return -1;
  1051. }
  1052. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1053. err("sohci_submit_job failed");
  1054. return -1;
  1055. }
  1056. wait_ms(10);
  1057. /* ohci_dump_status(&gohci); */
  1058. /* allow more time for a BULK device to react - some are slow */
  1059. #define BULK_TO 5000 /* timeout in milliseconds */
  1060. if (usb_pipetype (pipe) == PIPE_BULK)
  1061. timeout = BULK_TO;
  1062. else
  1063. timeout = 100;
  1064. /* wait for it to complete */
  1065. for (;;) {
  1066. /* check whether the controller is done */
  1067. stat = hc_interrupt();
  1068. if (stat < 0) {
  1069. stat = USB_ST_CRC_ERR;
  1070. break;
  1071. }
  1072. if (stat >= 0 && stat != 0xff) {
  1073. /* 0xff is returned for an SF-interrupt */
  1074. break;
  1075. }
  1076. if (--timeout) {
  1077. wait_ms(1);
  1078. } else {
  1079. err("CTL:TIMEOUT ");
  1080. stat = USB_ST_CRC_ERR;
  1081. break;
  1082. }
  1083. }
  1084. /* we got an Root Hub Status Change interrupt */
  1085. if (got_rhsc) {
  1086. #ifdef DEBUG
  1087. ohci_dump_roothub (&gohci, 1);
  1088. #endif
  1089. got_rhsc = 0;
  1090. /* abuse timeout */
  1091. timeout = rh_check_port_status(&gohci);
  1092. if (timeout >= 0) {
  1093. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1094. /* the called routine adds 1 to the passed value */
  1095. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1096. #endif
  1097. /*
  1098. * XXX
  1099. * This is potentially dangerous because it assumes
  1100. * that only one device is ever plugged in!
  1101. */
  1102. devgone = dev;
  1103. }
  1104. }
  1105. dev->status = stat;
  1106. dev->act_len = transfer_len;
  1107. #ifdef DEBUG
  1108. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1109. #else
  1110. wait_ms(1);
  1111. #endif
  1112. /* free TDs in urb_priv */
  1113. urb_free_priv (&urb_priv);
  1114. return 0;
  1115. }
  1116. /* submit routines called from usb.c */
  1117. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1118. int transfer_len)
  1119. {
  1120. info("submit_bulk_msg");
  1121. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1122. }
  1123. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1124. int transfer_len, struct devrequest *setup)
  1125. {
  1126. int maxsize = usb_maxpacket(dev, pipe);
  1127. info("submit_control_msg");
  1128. #ifdef DEBUG
  1129. urb_priv.actual_length = 0;
  1130. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1131. #else
  1132. wait_ms(1);
  1133. #endif
  1134. if (!maxsize) {
  1135. err("submit_control_message: pipesize for pipe %lx is zero",
  1136. pipe);
  1137. return -1;
  1138. }
  1139. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1140. gohci.rh.dev = dev;
  1141. /* root hub - redirect */
  1142. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1143. setup);
  1144. }
  1145. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1146. }
  1147. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1148. int transfer_len, int interval)
  1149. {
  1150. info("submit_int_msg");
  1151. return -1;
  1152. }
  1153. /*-------------------------------------------------------------------------*
  1154. * HC functions
  1155. *-------------------------------------------------------------------------*/
  1156. /* reset the HC and BUS */
  1157. static int hc_reset (ohci_t *ohci)
  1158. {
  1159. int timeout = 30;
  1160. int smm_timeout = 50; /* 0,5 sec */
  1161. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1162. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1163. info("USB HC TakeOver from SMM");
  1164. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1165. wait_ms (10);
  1166. if (--smm_timeout == 0) {
  1167. err("USB HC TakeOver failed!");
  1168. return -1;
  1169. }
  1170. }
  1171. }
  1172. /* Disable HC interrupts */
  1173. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1174. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1175. ohci->slot_name,
  1176. readl (&ohci->regs->control));
  1177. /* Reset USB (needed by some controllers) */
  1178. writel (0, &ohci->regs->control);
  1179. /* HC Reset requires max 10 us delay */
  1180. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1181. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1182. if (--timeout == 0) {
  1183. err("USB HC reset timed out!");
  1184. return -1;
  1185. }
  1186. udelay (1);
  1187. }
  1188. return 0;
  1189. }
  1190. /*-------------------------------------------------------------------------*/
  1191. /* Start an OHCI controller, set the BUS operational
  1192. * enable interrupts
  1193. * connect the virtual root hub */
  1194. static int hc_start (ohci_t * ohci)
  1195. {
  1196. __u32 mask;
  1197. unsigned int fminterval;
  1198. ohci->disabled = 1;
  1199. /* Tell the controller where the control and bulk lists are
  1200. * The lists are empty now. */
  1201. writel (0, &ohci->regs->ed_controlhead);
  1202. writel (0, &ohci->regs->ed_bulkhead);
  1203. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1204. fminterval = 0x2edf;
  1205. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1206. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1207. writel (fminterval, &ohci->regs->fminterval);
  1208. writel (0x628, &ohci->regs->lsthresh);
  1209. /* start controller operations */
  1210. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1211. ohci->disabled = 0;
  1212. writel (ohci->hc_control, &ohci->regs->control);
  1213. /* disable all interrupts */
  1214. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1215. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1216. OHCI_INTR_OC | OHCI_INTR_MIE);
  1217. writel (mask, &ohci->regs->intrdisable);
  1218. /* clear all interrupts */
  1219. mask &= ~OHCI_INTR_MIE;
  1220. writel (mask, &ohci->regs->intrstatus);
  1221. /* Choose the interrupts we care about now - but w/o MIE */
  1222. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1223. writel (mask, &ohci->regs->intrenable);
  1224. #ifdef OHCI_USE_NPS
  1225. /* required for AMD-756 and some Mac platforms */
  1226. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1227. &ohci->regs->roothub.a);
  1228. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1229. #endif /* OHCI_USE_NPS */
  1230. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1231. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1232. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1233. /* connect the virtual root hub */
  1234. ohci->rh.devnum = 0;
  1235. return 0;
  1236. }
  1237. /*-------------------------------------------------------------------------*/
  1238. /* an interrupt happens */
  1239. static int
  1240. hc_interrupt (void)
  1241. {
  1242. ohci_t *ohci = &gohci;
  1243. struct ohci_regs *regs = ohci->regs;
  1244. int ints;
  1245. int stat = -1;
  1246. if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1247. ints = OHCI_INTR_WDH;
  1248. } else {
  1249. ints = readl (&regs->intrstatus);
  1250. }
  1251. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1252. if (ints & OHCI_INTR_RHSC) {
  1253. got_rhsc = 1;
  1254. }
  1255. if (ints & OHCI_INTR_UE) {
  1256. ohci->disabled++;
  1257. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1258. ohci->slot_name);
  1259. /* e.g. due to PCI Master/Target Abort */
  1260. #ifdef DEBUG
  1261. ohci_dump (ohci, 1);
  1262. #else
  1263. wait_ms(1);
  1264. #endif
  1265. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1266. /* Make some non-interrupt context restart the controller. */
  1267. /* Count and limit the retries though; either hardware or */
  1268. /* software errors can go forever... */
  1269. hc_reset (ohci);
  1270. return -1;
  1271. }
  1272. if (ints & OHCI_INTR_WDH) {
  1273. wait_ms(1);
  1274. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1275. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1276. writel (OHCI_INTR_WDH, &regs->intrenable);
  1277. }
  1278. if (ints & OHCI_INTR_SO) {
  1279. dbg("USB Schedule overrun\n");
  1280. writel (OHCI_INTR_SO, &regs->intrenable);
  1281. stat = -1;
  1282. }
  1283. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1284. if (ints & OHCI_INTR_SF) {
  1285. unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
  1286. wait_ms(1);
  1287. writel (OHCI_INTR_SF, &regs->intrdisable);
  1288. if (ohci->ed_rm_list[frame] != NULL)
  1289. writel (OHCI_INTR_SF, &regs->intrenable);
  1290. stat = 0xff;
  1291. }
  1292. writel (ints, &regs->intrstatus);
  1293. return stat;
  1294. }
  1295. /*-------------------------------------------------------------------------*/
  1296. /*-------------------------------------------------------------------------*/
  1297. /* De-allocate all resources.. */
  1298. static void hc_release_ohci (ohci_t *ohci)
  1299. {
  1300. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1301. if (!ohci->disabled)
  1302. hc_reset (ohci);
  1303. }
  1304. /*-------------------------------------------------------------------------*/
  1305. /*
  1306. * low level initalisation routine, called from usb.c
  1307. */
  1308. static char ohci_inited = 0;
  1309. int usb_lowlevel_init(void)
  1310. {
  1311. S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  1312. S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  1313. /*
  1314. * Set the 48 MHz UPLL clocking. Values are taken from
  1315. * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
  1316. */
  1317. clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
  1318. gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
  1319. /*
  1320. * Enable USB host clock.
  1321. */
  1322. clk_power->CLKCON |= (1 << 4);
  1323. memset (&gohci, 0, sizeof (ohci_t));
  1324. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1325. /* align the storage */
  1326. if ((__u32)&ghcca[0] & 0xff) {
  1327. err("HCCA not aligned!!");
  1328. return -1;
  1329. }
  1330. phcca = &ghcca[0];
  1331. info("aligned ghcca %p", phcca);
  1332. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1333. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1334. err("EDs not aligned!!");
  1335. return -1;
  1336. }
  1337. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1338. if ((__u32)gtd & 0x7) {
  1339. err("TDs not aligned!!");
  1340. return -1;
  1341. }
  1342. ptd = gtd;
  1343. gohci.hcca = phcca;
  1344. memset (phcca, 0, sizeof (struct ohci_hcca));
  1345. gohci.disabled = 1;
  1346. gohci.sleeping = 0;
  1347. gohci.irq = -1;
  1348. gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
  1349. gohci.flags = 0;
  1350. gohci.slot_name = "s3c2400";
  1351. if (hc_reset (&gohci) < 0) {
  1352. hc_release_ohci (&gohci);
  1353. /* Initialization failed */
  1354. clk_power->CLKCON &= ~(1 << 4);
  1355. return -1;
  1356. }
  1357. /* FIXME this is a second HC reset; why?? */
  1358. writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
  1359. wait_ms (10);
  1360. if (hc_start (&gohci) < 0) {
  1361. err ("can't start usb-%s", gohci.slot_name);
  1362. hc_release_ohci (&gohci);
  1363. /* Initialization failed */
  1364. clk_power->CLKCON &= ~(1 << 4);
  1365. return -1;
  1366. }
  1367. #ifdef DEBUG
  1368. ohci_dump (&gohci, 1);
  1369. #else
  1370. wait_ms(1);
  1371. #endif
  1372. ohci_inited = 1;
  1373. return 0;
  1374. }
  1375. int usb_lowlevel_stop(void)
  1376. {
  1377. S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  1378. /* this gets called really early - before the controller has */
  1379. /* even been initialized! */
  1380. if (!ohci_inited)
  1381. return 0;
  1382. /* TODO release any interrupts, etc. */
  1383. /* call hc_release_ohci() here ? */
  1384. hc_reset (&gohci);
  1385. /* may not want to do this */
  1386. clk_power->CLKCON &= ~(1 << 4);
  1387. return 0;
  1388. }
  1389. #endif /* CONFIG_USB_OHCI */