fsl_law.h 2.7 KB

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  1. /*
  2. * Copyright 2008-2009 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #ifndef _FSL_LAW_H_
  9. #define _FSL_LAW_H_
  10. #include <asm/io.h>
  11. #define LAW_EN 0x80000000
  12. #define SET_LAW_ENTRY(idx, a, sz, trgt) \
  13. { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
  14. #define SET_LAW(a, sz, trgt) \
  15. { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
  16. enum law_size {
  17. LAW_SIZE_4K = 0xb,
  18. LAW_SIZE_8K,
  19. LAW_SIZE_16K,
  20. LAW_SIZE_32K,
  21. LAW_SIZE_64K,
  22. LAW_SIZE_128K,
  23. LAW_SIZE_256K,
  24. LAW_SIZE_512K,
  25. LAW_SIZE_1M,
  26. LAW_SIZE_2M,
  27. LAW_SIZE_4M,
  28. LAW_SIZE_8M,
  29. LAW_SIZE_16M,
  30. LAW_SIZE_32M,
  31. LAW_SIZE_64M,
  32. LAW_SIZE_128M,
  33. LAW_SIZE_256M,
  34. LAW_SIZE_512M,
  35. LAW_SIZE_1G,
  36. LAW_SIZE_2G,
  37. LAW_SIZE_4G,
  38. LAW_SIZE_8G,
  39. LAW_SIZE_16G,
  40. LAW_SIZE_32G,
  41. };
  42. #ifdef CONFIG_FSL_CORENET
  43. enum law_trgt_if {
  44. LAW_TRGT_IF_PCIE_1 = 0x00,
  45. LAW_TRGT_IF_PCIE_2 = 0x01,
  46. LAW_TRGT_IF_PCIE_3 = 0x02,
  47. LAW_TRGT_IF_RIO_1 = 0x08,
  48. LAW_TRGT_IF_RIO_2 = 0x09,
  49. LAW_TRGT_IF_DDR_1 = 0x10,
  50. LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
  51. LAW_TRGT_IF_DDR_INTRLV = 0x14,
  52. LAW_TRGT_IF_BMAN = 0x18,
  53. LAW_TRGT_IF_DCSR = 0x1d,
  54. LAW_TRGT_IF_LBC = 0x1f,
  55. LAW_TRGT_IF_QMAN = 0x3c,
  56. };
  57. #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
  58. #else
  59. enum law_trgt_if {
  60. LAW_TRGT_IF_PCI = 0x00,
  61. LAW_TRGT_IF_PCI_2 = 0x01,
  62. #ifndef CONFIG_MPC8641
  63. LAW_TRGT_IF_PCIE_1 = 0x02,
  64. #endif
  65. #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
  66. LAW_TRGT_IF_PCIE_3 = 0x03,
  67. #endif
  68. LAW_TRGT_IF_LBC = 0x04,
  69. LAW_TRGT_IF_CCSR = 0x08,
  70. LAW_TRGT_IF_DDR_INTRLV = 0x0b,
  71. LAW_TRGT_IF_RIO = 0x0c,
  72. LAW_TRGT_IF_DDR = 0x0f,
  73. LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
  74. };
  75. #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
  76. #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
  77. #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
  78. #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
  79. #ifdef CONFIG_MPC8641
  80. #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
  81. #endif
  82. #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
  83. #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
  84. #endif
  85. #endif /* CONFIG_FSL_CORENET */
  86. struct law_entry {
  87. int index;
  88. phys_addr_t addr;
  89. enum law_size size;
  90. enum law_trgt_if trgt_id;
  91. };
  92. extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
  93. extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
  94. extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
  95. extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
  96. extern struct law_entry find_law(phys_addr_t addr);
  97. extern void disable_law(u8 idx);
  98. extern void init_laws(void);
  99. extern void print_laws(void);
  100. /* define in board code */
  101. extern struct law_entry law_table[];
  102. extern int num_law_entries;
  103. #endif