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asm-blackfin
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cplb.h

cplb.h 3.9 KB
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  1. /************************************************************************
    2. 

  2.  *
    3. 

  3.  * cplb.h
    4. 

  4.  *
    5. 

  5.  * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
    6. 

  6.  *
    7. 

  7.  ************************************************************************/
    8. 

  8. 

  9. /* Defines necessary for cplb initialisation routines. */
    10. 

  10. #ifndef _CPLB_H
    11. 

  11. #define _CPLB_H
    12. 

  12. 

  13. #define CONFIG_BLKFIN_WT
    14. 

  14. 

  15. #define CPLB_ENABLE_ICACHE_P	0
    16. 

  16. #define CPLB_ENABLE_DCACHE_P	1
    17. 

  17. #define CPLB_ENABLE_DCACHE2_P	2
    18. 

  18. #define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
    19. 

  19. #define CPLB_ENABLE_ICPLBS_P	4
    20. 

  20. #define CPLB_ENABLE_DCPLBS_P	5
    21. 

  21. 

  22. #define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
    23. 

  23. #define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
    24. 

  24. #define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
    25. 

  25. #define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
    26. 

  26. #define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
    27. 

  27. #define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
    28. 

  28. #define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
    29. 

  29. 				CPLB_ENABLE_ICPLBS | \
    30. 

  30. 				CPLB_ENABLE_DCPLBS
    31. 

  31. 

  32. #define CPLB_RELOADED		0x0000
    33. 

  33. #define CPLB_NO_UNLOCKED	0x0001
    34. 

  34. #define CPLB_NO_ADDR_MATCH	0x0002
    35. 

  35. #define CPLB_PROT_VIOL		0x0003
    36. 

  36. 

  37. #define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
    38. 

  38. #define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY
    39. 

  39. 

  40. #define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
    41. 

  41. 

  42. #define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
    43. 

  43. #define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
    44. 

  44. #define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
    45. 

  45. #define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
    46. 

  46. #define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
    47. 

  47. #define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL
    48. 

  48. 

  49. /* Data Attibutes*/
    50. 

  50. 

  51. #define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
    52. 

  52. #define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
    53. 

  53. #define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
    54. 

  54. #define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
    55. 

  55. 

  56. /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
    57. 

  57. 

  58. #define ANOMALY_05000158                0x200
    59. 

  59. 

  60. #ifdef CONFIG_BLKFIN_WB		/*Write Back Policy */
    61. 

  61. #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
    62. 

  62. #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
    63. 

  63. #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
    64. 

  64. #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
    65. 

  65. #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
    66. 

  66. 

  67. #else				/*Write Through */
    68. 

  68. #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
    69. 

  69. #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
    70. 

  70. #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
    71. 

  71. #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
    72. 

  72. #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
    73. 

  73. #endif
    74. 

  74. 

  75. #if defined(CONFIG_BF561)
    76. 

  76. #define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2)	/* SDRAM +L1 + ASYNC_Memory */
    77. 

  77. #else
    78. 

  78. #define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3)	/* SDRAM + L1 + ASYNC_Memory */
    79. 

  79. #endif
    80. 

  80. #endif				/* _CPLB_H */
    81.