ehci-hcd.c 22 KB

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  1. /*-
  2. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  3. * Copyright (c) 2008, Excito Elektronik i Skåne AB
  4. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2 of
  11. * the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/byteorder.h>
  25. #include <usb.h>
  26. #include <asm/io.h>
  27. #include <malloc.h>
  28. #include <watchdog.h>
  29. #include "ehci.h"
  30. int rootdev;
  31. struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  32. volatile struct ehci_hcor *hcor;
  33. static uint16_t portreset;
  34. static struct QH qh_list __attribute__((aligned(32)));
  35. static struct descriptor {
  36. struct usb_hub_descriptor hub;
  37. struct usb_device_descriptor device;
  38. struct usb_linux_config_descriptor config;
  39. struct usb_linux_interface_descriptor interface;
  40. struct usb_endpoint_descriptor endpoint;
  41. } __attribute__ ((packed)) descriptor = {
  42. {
  43. 0x8, /* bDescLength */
  44. 0x29, /* bDescriptorType: hub descriptor */
  45. 2, /* bNrPorts -- runtime modified */
  46. 0, /* wHubCharacteristics */
  47. 0xff, /* bPwrOn2PwrGood */
  48. 0, /* bHubCntrCurrent */
  49. {}, /* Device removable */
  50. {} /* at most 7 ports! XXX */
  51. },
  52. {
  53. 0x12, /* bLength */
  54. 1, /* bDescriptorType: UDESC_DEVICE */
  55. cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  56. 9, /* bDeviceClass: UDCLASS_HUB */
  57. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  58. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  59. 64, /* bMaxPacketSize: 64 bytes */
  60. 0x0000, /* idVendor */
  61. 0x0000, /* idProduct */
  62. cpu_to_le16(0x0100), /* bcdDevice */
  63. 1, /* iManufacturer */
  64. 2, /* iProduct */
  65. 0, /* iSerialNumber */
  66. 1 /* bNumConfigurations: 1 */
  67. },
  68. {
  69. 0x9,
  70. 2, /* bDescriptorType: UDESC_CONFIG */
  71. cpu_to_le16(0x19),
  72. 1, /* bNumInterface */
  73. 1, /* bConfigurationValue */
  74. 0, /* iConfiguration */
  75. 0x40, /* bmAttributes: UC_SELF_POWER */
  76. 0 /* bMaxPower */
  77. },
  78. {
  79. 0x9, /* bLength */
  80. 4, /* bDescriptorType: UDESC_INTERFACE */
  81. 0, /* bInterfaceNumber */
  82. 0, /* bAlternateSetting */
  83. 1, /* bNumEndpoints */
  84. 9, /* bInterfaceClass: UICLASS_HUB */
  85. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  86. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  87. 0 /* iInterface */
  88. },
  89. {
  90. 0x7, /* bLength */
  91. 5, /* bDescriptorType: UDESC_ENDPOINT */
  92. 0x81, /* bEndpointAddress:
  93. * UE_DIR_IN | EHCI_INTR_ENDPT
  94. */
  95. 3, /* bmAttributes: UE_INTERRUPT */
  96. 8, /* wMaxPacketSize */
  97. 255 /* bInterval */
  98. },
  99. };
  100. #if defined(CONFIG_EHCI_IS_TDI)
  101. #define ehci_is_TDI() (1)
  102. #else
  103. #define ehci_is_TDI() (0)
  104. #endif
  105. #if defined(CONFIG_EHCI_DCACHE)
  106. /*
  107. * Routines to handle (flush/invalidate) the dcache for the QH and qTD
  108. * structures and data buffers. This is needed on platforms using this
  109. * EHCI support with dcache enabled.
  110. */
  111. static void flush_invalidate(u32 addr, int size, int flush)
  112. {
  113. if (flush)
  114. flush_dcache_range(addr, addr + size);
  115. else
  116. invalidate_dcache_range(addr, addr + size);
  117. }
  118. static void cache_qtd(struct qTD *qtd, int flush)
  119. {
  120. u32 *ptr = (u32 *)qtd->qt_buffer[0];
  121. int len = (qtd->qt_token & 0x7fff0000) >> 16;
  122. flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
  123. if (ptr && len)
  124. flush_invalidate((u32)ptr, len, flush);
  125. }
  126. static inline struct QH *qh_addr(struct QH *qh)
  127. {
  128. return (struct QH *)((u32)qh & 0xffffffe0);
  129. }
  130. static void cache_qh(struct QH *qh, int flush)
  131. {
  132. struct qTD *qtd;
  133. struct qTD *next;
  134. static struct qTD *first_qtd;
  135. /*
  136. * Walk the QH list and flush/invalidate all entries
  137. */
  138. while (1) {
  139. flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
  140. if ((u32)qh & QH_LINK_TYPE_QH)
  141. break;
  142. qh = qh_addr(qh);
  143. qh = (struct QH *)qh->qh_link;
  144. }
  145. qh = qh_addr(qh);
  146. /*
  147. * Save first qTD pointer, needed for invalidating pass on this QH
  148. */
  149. if (flush)
  150. first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
  151. 0xffffffe0);
  152. else
  153. qtd = first_qtd;
  154. /*
  155. * Walk the qTD list and flush/invalidate all entries
  156. */
  157. while (1) {
  158. if (qtd == NULL)
  159. break;
  160. cache_qtd(qtd, flush);
  161. next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
  162. if (next == qtd)
  163. break;
  164. qtd = next;
  165. }
  166. }
  167. static inline void ehci_flush_dcache(struct QH *qh)
  168. {
  169. cache_qh(qh, 1);
  170. }
  171. static inline void ehci_invalidate_dcache(struct QH *qh)
  172. {
  173. cache_qh(qh, 0);
  174. }
  175. #else /* CONFIG_EHCI_DCACHE */
  176. /*
  177. *
  178. */
  179. static inline void ehci_flush_dcache(struct QH *qh)
  180. {
  181. }
  182. static inline void ehci_invalidate_dcache(struct QH *qh)
  183. {
  184. }
  185. #endif /* CONFIG_EHCI_DCACHE */
  186. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
  187. {
  188. uint32_t result;
  189. do {
  190. result = ehci_readl(ptr);
  191. udelay(5);
  192. if (result == ~(uint32_t)0)
  193. return -1;
  194. result &= mask;
  195. if (result == done)
  196. return 0;
  197. usec--;
  198. } while (usec > 0);
  199. return -1;
  200. }
  201. static void ehci_free(void *p, size_t sz)
  202. {
  203. }
  204. static int ehci_reset(void)
  205. {
  206. uint32_t cmd;
  207. uint32_t tmp;
  208. uint32_t *reg_ptr;
  209. int ret = 0;
  210. cmd = ehci_readl(&hcor->or_usbcmd);
  211. cmd = (cmd & ~CMD_RUN) | CMD_RESET;
  212. ehci_writel(&hcor->or_usbcmd, cmd);
  213. ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
  214. if (ret < 0) {
  215. printf("EHCI fail to reset\n");
  216. goto out;
  217. }
  218. if (ehci_is_TDI()) {
  219. reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
  220. tmp = ehci_readl(reg_ptr);
  221. tmp |= USBMODE_CM_HC;
  222. #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
  223. tmp |= USBMODE_BE;
  224. #endif
  225. ehci_writel(reg_ptr, tmp);
  226. }
  227. out:
  228. return ret;
  229. }
  230. static void *ehci_alloc(size_t sz, size_t align)
  231. {
  232. static struct QH qh __attribute__((aligned(32)));
  233. static struct qTD td[3] __attribute__((aligned (32)));
  234. static int ntds;
  235. void *p;
  236. switch (sz) {
  237. case sizeof(struct QH):
  238. p = &qh;
  239. ntds = 0;
  240. break;
  241. case sizeof(struct qTD):
  242. if (ntds == 3) {
  243. debug("out of TDs\n");
  244. return NULL;
  245. }
  246. p = &td[ntds];
  247. ntds++;
  248. break;
  249. default:
  250. debug("unknown allocation size\n");
  251. return NULL;
  252. }
  253. memset(p, 0, sz);
  254. return p;
  255. }
  256. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  257. {
  258. uint32_t addr, delta, next;
  259. int idx;
  260. addr = (uint32_t) buf;
  261. idx = 0;
  262. while (idx < 5) {
  263. td->qt_buffer[idx] = cpu_to_hc32(addr);
  264. td->qt_buffer_hi[idx] = 0;
  265. next = (addr + 4096) & ~4095;
  266. delta = next - addr;
  267. if (delta >= sz)
  268. break;
  269. sz -= delta;
  270. addr = next;
  271. idx++;
  272. }
  273. if (idx == 5) {
  274. debug("out of buffer pointers (%u bytes left)\n", sz);
  275. return -1;
  276. }
  277. return 0;
  278. }
  279. static int
  280. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  281. int length, struct devrequest *req)
  282. {
  283. struct QH *qh;
  284. struct qTD *td;
  285. volatile struct qTD *vtd;
  286. unsigned long ts;
  287. uint32_t *tdp;
  288. uint32_t endpt, token, usbsts;
  289. uint32_t c, toggle;
  290. uint32_t cmd;
  291. int timeout;
  292. int ret = 0;
  293. debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  294. buffer, length, req);
  295. if (req != NULL)
  296. debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  297. req->request, req->request,
  298. req->requesttype, req->requesttype,
  299. le16_to_cpu(req->value), le16_to_cpu(req->value),
  300. le16_to_cpu(req->index));
  301. qh = ehci_alloc(sizeof(struct QH), 32);
  302. if (qh == NULL) {
  303. debug("unable to allocate QH\n");
  304. return -1;
  305. }
  306. qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  307. c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
  308. usb_pipeendpoint(pipe) == 0) ? 1 : 0;
  309. endpt = (8 << 28) |
  310. (c << 27) |
  311. (usb_maxpacket(dev, pipe) << 16) |
  312. (0 << 15) |
  313. (1 << 14) |
  314. (usb_pipespeed(pipe) << 12) |
  315. (usb_pipeendpoint(pipe) << 8) |
  316. (0 << 7) | (usb_pipedevice(pipe) << 0);
  317. qh->qh_endpt1 = cpu_to_hc32(endpt);
  318. endpt = (1 << 30) |
  319. (dev->portnr << 23) |
  320. (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
  321. qh->qh_endpt2 = cpu_to_hc32(endpt);
  322. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  323. td = NULL;
  324. tdp = &qh->qh_overlay.qt_next;
  325. toggle =
  326. usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  327. if (req != NULL) {
  328. td = ehci_alloc(sizeof(struct qTD), 32);
  329. if (td == NULL) {
  330. debug("unable to allocate SETUP td\n");
  331. goto fail;
  332. }
  333. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  334. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  335. token = (0 << 31) |
  336. (sizeof(*req) << 16) |
  337. (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
  338. td->qt_token = cpu_to_hc32(token);
  339. if (ehci_td_buffer(td, req, sizeof(*req)) != 0) {
  340. debug("unable construct SETUP td\n");
  341. ehci_free(td, sizeof(*td));
  342. goto fail;
  343. }
  344. *tdp = cpu_to_hc32((uint32_t) td);
  345. tdp = &td->qt_next;
  346. toggle = 1;
  347. }
  348. if (length > 0 || req == NULL) {
  349. td = ehci_alloc(sizeof(struct qTD), 32);
  350. if (td == NULL) {
  351. debug("unable to allocate DATA td\n");
  352. goto fail;
  353. }
  354. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  355. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  356. token = (toggle << 31) |
  357. (length << 16) |
  358. ((req == NULL ? 1 : 0) << 15) |
  359. (0 << 12) |
  360. (3 << 10) |
  361. ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
  362. td->qt_token = cpu_to_hc32(token);
  363. if (ehci_td_buffer(td, buffer, length) != 0) {
  364. debug("unable construct DATA td\n");
  365. ehci_free(td, sizeof(*td));
  366. goto fail;
  367. }
  368. *tdp = cpu_to_hc32((uint32_t) td);
  369. tdp = &td->qt_next;
  370. }
  371. if (req != NULL) {
  372. td = ehci_alloc(sizeof(struct qTD), 32);
  373. if (td == NULL) {
  374. debug("unable to allocate ACK td\n");
  375. goto fail;
  376. }
  377. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  378. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  379. token = (toggle << 31) |
  380. (0 << 16) |
  381. (1 << 15) |
  382. (0 << 12) |
  383. (3 << 10) |
  384. ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
  385. td->qt_token = cpu_to_hc32(token);
  386. *tdp = cpu_to_hc32((uint32_t) td);
  387. tdp = &td->qt_next;
  388. }
  389. qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
  390. /* Flush dcache */
  391. ehci_flush_dcache(&qh_list);
  392. usbsts = ehci_readl(&hcor->or_usbsts);
  393. ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
  394. /* Enable async. schedule. */
  395. cmd = ehci_readl(&hcor->or_usbcmd);
  396. cmd |= CMD_ASE;
  397. ehci_writel(&hcor->or_usbcmd, cmd);
  398. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
  399. 100 * 1000);
  400. if (ret < 0) {
  401. printf("EHCI fail timeout STD_ASS set\n");
  402. goto fail;
  403. }
  404. /* Wait for TDs to be processed. */
  405. ts = get_timer(0);
  406. vtd = td;
  407. timeout = USB_TIMEOUT_MS(pipe);
  408. do {
  409. /* Invalidate dcache */
  410. ehci_invalidate_dcache(&qh_list);
  411. token = hc32_to_cpu(vtd->qt_token);
  412. if (!(token & 0x80))
  413. break;
  414. WATCHDOG_RESET();
  415. } while (get_timer(ts) < timeout);
  416. /* Check that the TD processing happened */
  417. if (token & 0x80) {
  418. printf("EHCI timed out on TD - token=%#x\n", token);
  419. }
  420. /* Disable async schedule. */
  421. cmd = ehci_readl(&hcor->or_usbcmd);
  422. cmd &= ~CMD_ASE;
  423. ehci_writel(&hcor->or_usbcmd, cmd);
  424. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
  425. 100 * 1000);
  426. if (ret < 0) {
  427. printf("EHCI fail timeout STD_ASS reset\n");
  428. goto fail;
  429. }
  430. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  431. token = hc32_to_cpu(qh->qh_overlay.qt_token);
  432. if (!(token & 0x80)) {
  433. debug("TOKEN=%#x\n", token);
  434. switch (token & 0xfc) {
  435. case 0:
  436. toggle = token >> 31;
  437. usb_settoggle(dev, usb_pipeendpoint(pipe),
  438. usb_pipeout(pipe), toggle);
  439. dev->status = 0;
  440. break;
  441. case 0x40:
  442. dev->status = USB_ST_STALLED;
  443. break;
  444. case 0xa0:
  445. case 0x20:
  446. dev->status = USB_ST_BUF_ERR;
  447. break;
  448. case 0x50:
  449. case 0x10:
  450. dev->status = USB_ST_BABBLE_DET;
  451. break;
  452. default:
  453. dev->status = USB_ST_CRC_ERR;
  454. if ((token & 0x40) == 0x40)
  455. dev->status |= USB_ST_STALLED;
  456. break;
  457. }
  458. dev->act_len = length - ((token >> 16) & 0x7fff);
  459. } else {
  460. dev->act_len = 0;
  461. debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
  462. dev->devnum, ehci_readl(&hcor->or_usbsts),
  463. ehci_readl(&hcor->or_portsc[0]),
  464. ehci_readl(&hcor->or_portsc[1]));
  465. }
  466. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  467. fail:
  468. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  469. while (td != (void *)QT_NEXT_TERMINATE) {
  470. qh->qh_overlay.qt_next = td->qt_next;
  471. ehci_free(td, sizeof(*td));
  472. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  473. }
  474. ehci_free(qh, sizeof(*qh));
  475. return -1;
  476. }
  477. static inline int min3(int a, int b, int c)
  478. {
  479. if (b < a)
  480. a = b;
  481. if (c < a)
  482. a = c;
  483. return a;
  484. }
  485. int
  486. ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
  487. int length, struct devrequest *req)
  488. {
  489. uint8_t tmpbuf[4];
  490. u16 typeReq;
  491. void *srcptr = NULL;
  492. int len, srclen;
  493. uint32_t reg;
  494. uint32_t *status_reg;
  495. if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
  496. printf("The request port(%d) is not configured\n",
  497. le16_to_cpu(req->index) - 1);
  498. return -1;
  499. }
  500. status_reg = (uint32_t *)&hcor->or_portsc[
  501. le16_to_cpu(req->index) - 1];
  502. srclen = 0;
  503. debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  504. req->request, req->request,
  505. req->requesttype, req->requesttype,
  506. le16_to_cpu(req->value), le16_to_cpu(req->index));
  507. typeReq = req->request | req->requesttype << 8;
  508. switch (typeReq) {
  509. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  510. switch (le16_to_cpu(req->value) >> 8) {
  511. case USB_DT_DEVICE:
  512. debug("USB_DT_DEVICE request\n");
  513. srcptr = &descriptor.device;
  514. srclen = 0x12;
  515. break;
  516. case USB_DT_CONFIG:
  517. debug("USB_DT_CONFIG config\n");
  518. srcptr = &descriptor.config;
  519. srclen = 0x19;
  520. break;
  521. case USB_DT_STRING:
  522. debug("USB_DT_STRING config\n");
  523. switch (le16_to_cpu(req->value) & 0xff) {
  524. case 0: /* Language */
  525. srcptr = "\4\3\1\0";
  526. srclen = 4;
  527. break;
  528. case 1: /* Vendor */
  529. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  530. srclen = 14;
  531. break;
  532. case 2: /* Product */
  533. srcptr = "\52\3E\0H\0C\0I\0 "
  534. "\0H\0o\0s\0t\0 "
  535. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  536. srclen = 42;
  537. break;
  538. default:
  539. debug("unknown value DT_STRING %x\n",
  540. le16_to_cpu(req->value));
  541. goto unknown;
  542. }
  543. break;
  544. default:
  545. debug("unknown value %x\n", le16_to_cpu(req->value));
  546. goto unknown;
  547. }
  548. break;
  549. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  550. switch (le16_to_cpu(req->value) >> 8) {
  551. case USB_DT_HUB:
  552. debug("USB_DT_HUB config\n");
  553. srcptr = &descriptor.hub;
  554. srclen = 0x8;
  555. break;
  556. default:
  557. debug("unknown value %x\n", le16_to_cpu(req->value));
  558. goto unknown;
  559. }
  560. break;
  561. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  562. debug("USB_REQ_SET_ADDRESS\n");
  563. rootdev = le16_to_cpu(req->value);
  564. break;
  565. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  566. debug("USB_REQ_SET_CONFIGURATION\n");
  567. /* Nothing to do */
  568. break;
  569. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  570. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  571. tmpbuf[1] = 0;
  572. srcptr = tmpbuf;
  573. srclen = 2;
  574. break;
  575. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  576. memset(tmpbuf, 0, 4);
  577. reg = ehci_readl(status_reg);
  578. if (reg & EHCI_PS_CS)
  579. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  580. if (reg & EHCI_PS_PE)
  581. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  582. if (reg & EHCI_PS_SUSP)
  583. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  584. if (reg & EHCI_PS_OCA)
  585. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  586. if (reg & EHCI_PS_PR)
  587. tmpbuf[0] |= USB_PORT_STAT_RESET;
  588. if (reg & EHCI_PS_PP)
  589. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  590. if (ehci_is_TDI()) {
  591. switch ((reg >> 26) & 3) {
  592. case 0:
  593. break;
  594. case 1:
  595. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  596. break;
  597. case 2:
  598. default:
  599. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  600. break;
  601. }
  602. } else {
  603. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  604. }
  605. if (reg & EHCI_PS_CSC)
  606. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  607. if (reg & EHCI_PS_PEC)
  608. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  609. if (reg & EHCI_PS_OCC)
  610. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  611. if (portreset & (1 << le16_to_cpu(req->index)))
  612. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  613. srcptr = tmpbuf;
  614. srclen = 4;
  615. break;
  616. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  617. reg = ehci_readl(status_reg);
  618. reg &= ~EHCI_PS_CLEAR;
  619. switch (le16_to_cpu(req->value)) {
  620. case USB_PORT_FEAT_ENABLE:
  621. reg |= EHCI_PS_PE;
  622. ehci_writel(status_reg, reg);
  623. break;
  624. case USB_PORT_FEAT_POWER:
  625. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
  626. reg |= EHCI_PS_PP;
  627. ehci_writel(status_reg, reg);
  628. }
  629. break;
  630. case USB_PORT_FEAT_RESET:
  631. if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
  632. !ehci_is_TDI() &&
  633. EHCI_PS_IS_LOWSPEED(reg)) {
  634. /* Low speed device, give up ownership. */
  635. debug("port %d low speed --> companion\n",
  636. req->index - 1);
  637. reg |= EHCI_PS_PO;
  638. ehci_writel(status_reg, reg);
  639. break;
  640. } else {
  641. int ret;
  642. reg |= EHCI_PS_PR;
  643. reg &= ~EHCI_PS_PE;
  644. ehci_writel(status_reg, reg);
  645. /*
  646. * caller must wait, then call GetPortStatus
  647. * usb 2.0 specification say 50 ms resets on
  648. * root
  649. */
  650. wait_ms(50);
  651. /* terminate the reset */
  652. ehci_writel(status_reg, reg & ~EHCI_PS_PR);
  653. /*
  654. * A host controller must terminate the reset
  655. * and stabilize the state of the port within
  656. * 2 milliseconds
  657. */
  658. ret = handshake(status_reg, EHCI_PS_PR, 0,
  659. 2 * 1000);
  660. if (!ret)
  661. portreset |=
  662. 1 << le16_to_cpu(req->index);
  663. else
  664. printf("port(%d) reset error\n",
  665. le16_to_cpu(req->index) - 1);
  666. }
  667. break;
  668. default:
  669. debug("unknown feature %x\n", le16_to_cpu(req->value));
  670. goto unknown;
  671. }
  672. /* unblock posted writes */
  673. (void) ehci_readl(&hcor->or_usbcmd);
  674. break;
  675. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  676. reg = ehci_readl(status_reg);
  677. switch (le16_to_cpu(req->value)) {
  678. case USB_PORT_FEAT_ENABLE:
  679. reg &= ~EHCI_PS_PE;
  680. break;
  681. case USB_PORT_FEAT_C_ENABLE:
  682. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
  683. break;
  684. case USB_PORT_FEAT_POWER:
  685. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
  686. reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
  687. case USB_PORT_FEAT_C_CONNECTION:
  688. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
  689. break;
  690. case USB_PORT_FEAT_OVER_CURRENT:
  691. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
  692. break;
  693. case USB_PORT_FEAT_C_RESET:
  694. portreset &= ~(1 << le16_to_cpu(req->index));
  695. break;
  696. default:
  697. debug("unknown feature %x\n", le16_to_cpu(req->value));
  698. goto unknown;
  699. }
  700. ehci_writel(status_reg, reg);
  701. /* unblock posted write */
  702. (void) ehci_readl(&hcor->or_usbcmd);
  703. break;
  704. default:
  705. debug("Unknown request\n");
  706. goto unknown;
  707. }
  708. wait_ms(1);
  709. len = min3(srclen, le16_to_cpu(req->length), length);
  710. if (srcptr != NULL && len > 0)
  711. memcpy(buffer, srcptr, len);
  712. else
  713. debug("Len is 0\n");
  714. dev->act_len = len;
  715. dev->status = 0;
  716. return 0;
  717. unknown:
  718. debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  719. req->requesttype, req->request, le16_to_cpu(req->value),
  720. le16_to_cpu(req->index), le16_to_cpu(req->length));
  721. dev->act_len = 0;
  722. dev->status = USB_ST_STALLED;
  723. return -1;
  724. }
  725. int usb_lowlevel_stop(void)
  726. {
  727. return ehci_hcd_stop();
  728. }
  729. int usb_lowlevel_init(void)
  730. {
  731. uint32_t reg;
  732. uint32_t cmd;
  733. if (ehci_hcd_init() != 0)
  734. return -1;
  735. /* EHCI spec section 4.1 */
  736. if (ehci_reset() != 0)
  737. return -1;
  738. #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
  739. if (ehci_hcd_init() != 0)
  740. return -1;
  741. #endif
  742. /* Set head of reclaim list */
  743. memset(&qh_list, 0, sizeof(qh_list));
  744. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  745. qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
  746. qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
  747. qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  748. qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  749. qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
  750. /* Set async. queue head pointer. */
  751. ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
  752. reg = ehci_readl(&hccr->cr_hcsparams);
  753. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  754. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  755. /* Port Indicators */
  756. if (HCS_INDICATOR(reg))
  757. descriptor.hub.wHubCharacteristics |= 0x80;
  758. /* Port Power Control */
  759. if (HCS_PPC(reg))
  760. descriptor.hub.wHubCharacteristics |= 0x01;
  761. /* Start the host controller. */
  762. cmd = ehci_readl(&hcor->or_usbcmd);
  763. /*
  764. * Philips, Intel, and maybe others need CMD_RUN before the
  765. * root hub will detect new devices (why?); NEC doesn't
  766. */
  767. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  768. cmd |= CMD_RUN;
  769. ehci_writel(&hcor->or_usbcmd, cmd);
  770. /* take control over the ports */
  771. cmd = ehci_readl(&hcor->or_configflag);
  772. cmd |= FLAG_CF;
  773. ehci_writel(&hcor->or_configflag, cmd);
  774. /* unblock posted write */
  775. cmd = ehci_readl(&hcor->or_usbcmd);
  776. wait_ms(5);
  777. reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
  778. printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
  779. rootdev = 0;
  780. return 0;
  781. }
  782. int
  783. submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  784. int length)
  785. {
  786. if (usb_pipetype(pipe) != PIPE_BULK) {
  787. debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  788. return -1;
  789. }
  790. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  791. }
  792. int
  793. submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  794. int length, struct devrequest *setup)
  795. {
  796. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  797. debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
  798. return -1;
  799. }
  800. if (usb_pipedevice(pipe) == rootdev) {
  801. if (rootdev == 0)
  802. dev->speed = USB_SPEED_HIGH;
  803. return ehci_submit_root(dev, pipe, buffer, length, setup);
  804. }
  805. return ehci_submit_async(dev, pipe, buffer, length, setup);
  806. }
  807. int
  808. submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  809. int length, int interval)
  810. {
  811. debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  812. dev, pipe, buffer, length, interval);
  813. return -1;
  814. }