sbc2410x.c 4.3 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Marius Groeger <mgroeger@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  8. *
  9. * (C) Copyright 2005
  10. * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #include <common.h>
  31. #include <netdev.h>
  32. #include <s3c2410.h>
  33. #if defined(CONFIG_CMD_NAND)
  34. #include <linux/mtd/nand.h>
  35. #endif
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #define FCLK_SPEED 1
  38. #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
  39. #define M_MDIV 0xC3
  40. #define M_PDIV 0x4
  41. #define M_SDIV 0x1
  42. #elif FCLK_SPEED==1 /* Fout = 202.8MHz */
  43. #define M_MDIV 0x5c
  44. #define M_PDIV 0x4
  45. #define M_SDIV 0x0
  46. #endif
  47. #define USB_CLOCK 1
  48. #if USB_CLOCK==0
  49. #define U_M_MDIV 0xA1
  50. #define U_M_PDIV 0x3
  51. #define U_M_SDIV 0x1
  52. #elif USB_CLOCK==1
  53. #define U_M_MDIV 0x48
  54. #define U_M_PDIV 0x3
  55. #define U_M_SDIV 0x2
  56. #endif
  57. static inline void delay (unsigned long loops)
  58. {
  59. __asm__ volatile ("1:\n"
  60. "subs %0, %1, #1\n"
  61. "bne 1b":"=r" (loops):"0" (loops));
  62. }
  63. /*
  64. * Miscellaneous platform dependent initialisations
  65. */
  66. int board_init (void)
  67. {
  68. S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  69. S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  70. /* to reduce PLL lock time, adjust the LOCKTIME register */
  71. clk_power->LOCKTIME = 0xFFFFFF;
  72. /* configure MPLL */
  73. clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
  74. /* some delay between MPLL and UPLL */
  75. delay (4000);
  76. /* configure UPLL */
  77. clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
  78. /* some delay between MPLL and UPLL */
  79. delay (8000);
  80. /* set up the I/O ports */
  81. gpio->GPACON = 0x007FFFFF;
  82. gpio->GPBCON = 0x00044556;
  83. gpio->GPBUP = 0x000007FF;
  84. gpio->GPCCON = 0xAAAAAAAA;
  85. gpio->GPCUP = 0x0000FFFF;
  86. gpio->GPDCON = 0xAAAAAAAA;
  87. gpio->GPDUP = 0x0000FFFF;
  88. gpio->GPECON = 0xAAAAAAAA;
  89. gpio->GPEUP = 0x0000FFFF;
  90. gpio->GPFCON = 0x000055AA;
  91. gpio->GPFUP = 0x000000FF;
  92. gpio->GPGCON = 0xFF95FF3A;
  93. gpio->GPGUP = 0x0000FFFF;
  94. gpio->GPHCON = 0x0016FAAA;
  95. gpio->GPHUP = 0x000007FF;
  96. gpio->EXTINT0=0x22222222;
  97. gpio->EXTINT1=0x22222222;
  98. gpio->EXTINT2=0x22222222;
  99. /* arch number of SMDK2410-Board */
  100. gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
  101. /* adress of boot parameters */
  102. gd->bd->bi_boot_params = 0x30000100;
  103. icache_enable();
  104. dcache_enable();
  105. return 0;
  106. }
  107. int dram_init (void)
  108. {
  109. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  110. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  111. return 0;
  112. }
  113. #if defined(CONFIG_CMD_NAND)
  114. extern ulong nand_probe(ulong physadr);
  115. static inline void NF_Reset(void)
  116. {
  117. int i;
  118. NF_SetCE(NFCE_LOW);
  119. NF_Cmd(0xFF); /* reset command */
  120. for(i = 0; i < 10; i++); /* tWB = 100ns. */
  121. NF_WaitRB(); /* wait 200~500us; */
  122. NF_SetCE(NFCE_HIGH);
  123. }
  124. static inline void NF_Init(void)
  125. {
  126. #if 1
  127. #define TACLS 0
  128. #define TWRPH0 3
  129. #define TWRPH1 0
  130. #else
  131. #define TACLS 0
  132. #define TWRPH0 4
  133. #define TWRPH1 2
  134. #endif
  135. NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
  136. /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
  137. /* 1 1 1 1, 1 xxx, r xxx, r xxx */
  138. /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
  139. NF_Reset();
  140. }
  141. void nand_init(void)
  142. {
  143. S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
  144. NF_Init();
  145. #ifdef DEBUG
  146. printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
  147. #endif
  148. printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
  149. }
  150. #endif
  151. #ifdef CONFIG_CMD_NET
  152. int board_eth_init(bd_t *bis)
  153. {
  154. int rc = 0;
  155. #ifdef CONFIG_CS8900
  156. rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
  157. #endif
  158. return rc;
  159. }
  160. #endif