cpu.c 15 KB

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  1. /*
  2. * (C) Copyright 2000-2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * m8xx.c
  25. *
  26. * CPU specific code
  27. *
  28. * written or collected and sometimes rewritten by
  29. * Magnus Damm <damm@bitsmart.com>
  30. *
  31. * minor modifications by
  32. * Wolfgang Denk <wd@denx.de>
  33. */
  34. #include <common.h>
  35. #include <watchdog.h>
  36. #include <command.h>
  37. #include <mpc8xx.h>
  38. #include <asm/cache.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. static char *cpu_warning = "\n " \
  41. "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
  42. #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
  43. !defined(CONFIG_MPC862))
  44. static int check_CPU (long clock, uint pvr, uint immr)
  45. {
  46. char *id_str =
  47. # if defined(CONFIG_MPC855)
  48. "PC855";
  49. # elif defined(CONFIG_MPC860P)
  50. "PC860P";
  51. # else
  52. NULL;
  53. # endif
  54. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  55. uint k, m;
  56. char buf[32];
  57. char pre = 'X';
  58. char *mid = "xx";
  59. char *suf;
  60. /* the highest 16 bits should be 0x0050 for a 860 */
  61. if ((pvr >> 16) != 0x0050)
  62. return -1;
  63. k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
  64. m = 0;
  65. suf = "";
  66. /*
  67. * Some boards use sockets so different CPUs can be used.
  68. * We have to check chip version in run time.
  69. */
  70. switch (k) {
  71. case 0x00020001: pre = 'P'; break;
  72. case 0x00030001: break;
  73. case 0x00120003: suf = "A"; break;
  74. case 0x00130003: suf = "A3"; break;
  75. case 0x00200004: suf = "B"; break;
  76. case 0x00300004: suf = "C"; break;
  77. case 0x00310004: suf = "C1"; m = 1; break;
  78. case 0x00200064: mid = "SR"; suf = "B"; break;
  79. case 0x00300065: mid = "SR"; suf = "C"; break;
  80. case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
  81. case 0x05010000: suf = "D3"; m = 1; break;
  82. case 0x05020000: suf = "D4"; m = 1; break;
  83. /* this value is not documented anywhere */
  84. case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
  85. /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
  86. case 0x08010004: /* Rev. A.0 */
  87. suf = "A";
  88. /* fall through */
  89. case 0x08000003: /* Rev. 0.3 */
  90. pre = 'M'; m = 1;
  91. if (id_str == NULL)
  92. id_str =
  93. # if defined(CONFIG_MPC852T)
  94. "PC852T";
  95. # elif defined(CONFIG_MPC859T)
  96. "PC859T";
  97. # elif defined(CONFIG_MPC859DSL)
  98. "PC859DSL";
  99. # elif defined(CONFIG_MPC866T)
  100. "PC866T";
  101. # else
  102. "PC866x"; /* Unknown chip from MPC866 family */
  103. # endif
  104. break;
  105. case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
  106. if (id_str == NULL)
  107. id_str = "PC885"; /* 870/875/880/885 */
  108. break;
  109. default: suf = NULL; break;
  110. }
  111. if (id_str == NULL)
  112. id_str = "PC86x"; /* Unknown 86x chip */
  113. if (suf)
  114. printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
  115. else
  116. printf ("unknown M%s (0x%08x)", id_str, k);
  117. #if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
  118. printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
  119. strmhz (buf, clock),
  120. CFG_8xx_CPUCLK_MIN / 1000000,
  121. ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
  122. CFG_8xx_CPUCLK_MAX / 1000000,
  123. ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
  124. );
  125. #else
  126. printf (" at %s MHz: ", strmhz (buf, clock));
  127. #endif
  128. printf ("%u kB I-Cache %u kB D-Cache",
  129. checkicache () >> 10,
  130. checkdcache () >> 10
  131. );
  132. /* do we have a FEC (860T/P or 852/859/866/885)? */
  133. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  134. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  135. printf (" FEC present");
  136. }
  137. if (!m) {
  138. puts (cpu_warning);
  139. }
  140. putc ('\n');
  141. #ifdef DEBUG
  142. if(clock != measure_gclk()) {
  143. printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
  144. }
  145. #endif
  146. return 0;
  147. }
  148. #elif defined(CONFIG_MPC862)
  149. static int check_CPU (long clock, uint pvr, uint immr)
  150. {
  151. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  152. uint k, m;
  153. char buf[32];
  154. char pre = 'X';
  155. char *mid = "xx";
  156. char *suf;
  157. /* the highest 16 bits should be 0x0050 for a 8xx */
  158. if ((pvr >> 16) != 0x0050)
  159. return -1;
  160. k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
  161. m = 0;
  162. switch (k) {
  163. /* this value is not documented anywhere */
  164. case 0x06000000: mid = "P"; suf = "0"; break;
  165. case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
  166. case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
  167. default: suf = NULL; break;
  168. }
  169. #ifndef CONFIG_MPC857
  170. if (suf)
  171. printf ("%cPC862%sZPnn%s", pre, mid, suf);
  172. else
  173. printf ("unknown MPC862 (0x%08x)", k);
  174. #else
  175. if (suf)
  176. printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
  177. else
  178. printf ("unknown MPC857 (0x%08x)", k);
  179. #endif
  180. printf (" at %s MHz:", strmhz (buf, clock));
  181. printf (" %u kB I-Cache", checkicache () >> 10);
  182. printf (" %u kB D-Cache", checkdcache () >> 10);
  183. /* lets check and see if we're running on a 862T (or P?) */
  184. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  185. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  186. printf (" FEC present");
  187. }
  188. if (!m) {
  189. puts (cpu_warning);
  190. }
  191. putc ('\n');
  192. return 0;
  193. }
  194. #elif defined(CONFIG_MPC823)
  195. static int check_CPU (long clock, uint pvr, uint immr)
  196. {
  197. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  198. uint k, m;
  199. char buf[32];
  200. char *suf;
  201. /* the highest 16 bits should be 0x0050 for a 8xx */
  202. if ((pvr >> 16) != 0x0050)
  203. return -1;
  204. k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
  205. m = 0;
  206. switch (k) {
  207. /* MPC823 */
  208. case 0x20000000: suf = "0"; break;
  209. case 0x20010000: suf = "0.1"; break;
  210. case 0x20020000: suf = "Z2/3"; break;
  211. case 0x20020001: suf = "Z3"; break;
  212. case 0x21000000: suf = "A"; break;
  213. case 0x21010000: suf = "B"; m = 1; break;
  214. case 0x21010001: suf = "B2"; m = 1; break;
  215. /* MPC823E */
  216. case 0x24010000: suf = NULL;
  217. puts ("PPC823EZTnnB2");
  218. m = 1;
  219. break;
  220. default:
  221. suf = NULL;
  222. printf ("unknown MPC823 (0x%08x)", k);
  223. break;
  224. }
  225. if (suf)
  226. printf ("PPC823ZTnn%s", suf);
  227. printf (" at %s MHz:", strmhz (buf, clock));
  228. printf (" %u kB I-Cache", checkicache () >> 10);
  229. printf (" %u kB D-Cache", checkdcache () >> 10);
  230. /* lets check and see if we're running on a 860T (or P?) */
  231. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  232. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  233. puts (" FEC present");
  234. }
  235. if (!m) {
  236. puts (cpu_warning);
  237. }
  238. putc ('\n');
  239. return 0;
  240. }
  241. #elif defined(CONFIG_MPC850)
  242. static int check_CPU (long clock, uint pvr, uint immr)
  243. {
  244. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  245. uint k, m;
  246. char buf[32];
  247. /* the highest 16 bits should be 0x0050 for a 8xx */
  248. if ((pvr >> 16) != 0x0050)
  249. return -1;
  250. k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
  251. m = 0;
  252. switch (k) {
  253. case 0x20020001:
  254. printf ("XPC850xxZT");
  255. break;
  256. case 0x21000065:
  257. printf ("XPC850xxZTA");
  258. break;
  259. case 0x21010067:
  260. printf ("XPC850xxZTB");
  261. m = 1;
  262. break;
  263. case 0x21020068:
  264. printf ("XPC850xxZTC");
  265. m = 1;
  266. break;
  267. default:
  268. printf ("unknown MPC850 (0x%08x)", k);
  269. }
  270. printf (" at %s MHz:", strmhz (buf, clock));
  271. printf (" %u kB I-Cache", checkicache () >> 10);
  272. printf (" %u kB D-Cache", checkdcache () >> 10);
  273. /* lets check and see if we're running on a 850T (or P?) */
  274. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  275. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  276. printf (" FEC present");
  277. }
  278. if (!m) {
  279. puts (cpu_warning);
  280. }
  281. putc ('\n');
  282. return 0;
  283. }
  284. #else
  285. #error CPU undefined
  286. #endif
  287. /* ------------------------------------------------------------------------- */
  288. int checkcpu (void)
  289. {
  290. ulong clock = gd->cpu_clk;
  291. uint immr = get_immr (0); /* Return full IMMR contents */
  292. uint pvr = get_pvr ();
  293. puts ("CPU: ");
  294. /* 850 has PARTNUM 20 */
  295. /* 801 has PARTNUM 10 */
  296. return check_CPU (clock, pvr, immr);
  297. }
  298. /* ------------------------------------------------------------------------- */
  299. /* L1 i-cache */
  300. /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
  301. /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
  302. int checkicache (void)
  303. {
  304. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  305. volatile memctl8xx_t *memctl = &immap->im_memctl;
  306. u32 cacheon = rd_ic_cst () & IDC_ENABLED;
  307. #ifdef CONFIG_IP86x
  308. u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
  309. #else
  310. u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
  311. #endif
  312. u32 m;
  313. u32 lines = -1;
  314. wr_ic_cst (IDC_UNALL);
  315. wr_ic_cst (IDC_INVALL);
  316. wr_ic_cst (IDC_DISABLE);
  317. __asm__ volatile ("isync");
  318. while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
  319. wr_ic_adr (k);
  320. wr_ic_cst (IDC_LDLCK);
  321. __asm__ volatile ("isync");
  322. lines++;
  323. k += 0x10; /* the number of bytes in a cacheline */
  324. }
  325. wr_ic_cst (IDC_UNALL);
  326. wr_ic_cst (IDC_INVALL);
  327. if (cacheon)
  328. wr_ic_cst (IDC_ENABLE);
  329. else
  330. wr_ic_cst (IDC_DISABLE);
  331. __asm__ volatile ("isync");
  332. return lines << 4;
  333. };
  334. /* ------------------------------------------------------------------------- */
  335. /* L1 d-cache */
  336. /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
  337. /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
  338. /* call with cache disabled */
  339. int checkdcache (void)
  340. {
  341. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  342. volatile memctl8xx_t *memctl = &immap->im_memctl;
  343. u32 cacheon = rd_dc_cst () & IDC_ENABLED;
  344. #ifdef CONFIG_IP86x
  345. u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
  346. #else
  347. u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
  348. #endif
  349. u32 m;
  350. u32 lines = -1;
  351. wr_dc_cst (IDC_UNALL);
  352. wr_dc_cst (IDC_INVALL);
  353. wr_dc_cst (IDC_DISABLE);
  354. while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
  355. wr_dc_adr (k);
  356. wr_dc_cst (IDC_LDLCK);
  357. lines++;
  358. k += 0x10; /* the number of bytes in a cacheline */
  359. }
  360. wr_dc_cst (IDC_UNALL);
  361. wr_dc_cst (IDC_INVALL);
  362. if (cacheon)
  363. wr_dc_cst (IDC_ENABLE);
  364. else
  365. wr_dc_cst (IDC_DISABLE);
  366. return lines << 4;
  367. };
  368. /* ------------------------------------------------------------------------- */
  369. void upmconfig (uint upm, uint * table, uint size)
  370. {
  371. uint i;
  372. uint addr = 0;
  373. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  374. volatile memctl8xx_t *memctl = &immap->im_memctl;
  375. for (i = 0; i < size; i++) {
  376. memctl->memc_mdr = table[i]; /* (16-15) */
  377. memctl->memc_mcr = addr | upm; /* (16-16) */
  378. addr++;
  379. }
  380. }
  381. /* ------------------------------------------------------------------------- */
  382. #ifndef CONFIG_LWMON
  383. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  384. {
  385. ulong msr, addr;
  386. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  387. immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
  388. /* Interrupts and MMU off */
  389. __asm__ volatile ("mtspr 81, 0");
  390. __asm__ volatile ("mfmsr %0":"=r" (msr));
  391. msr &= ~0x1030;
  392. __asm__ volatile ("mtmsr %0"::"r" (msr));
  393. /*
  394. * Trying to execute the next instruction at a non-existing address
  395. * should cause a machine check, resulting in reset
  396. */
  397. #ifdef CFG_RESET_ADDRESS
  398. addr = CFG_RESET_ADDRESS;
  399. #else
  400. /*
  401. * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
  402. * - sizeof (ulong) is usually a valid address. Better pick an address
  403. * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
  404. * "(ulong)-1" used to be a good choice for many systems...
  405. */
  406. addr = CFG_MONITOR_BASE - sizeof (ulong);
  407. #endif
  408. ((void (*)(void)) addr) ();
  409. return 1;
  410. }
  411. #else /* CONFIG_LWMON */
  412. /*
  413. * On the LWMON board, the MCLR reset input of the PIC's on the board
  414. * uses a 47K/1n RC combination which has a 47us time constant. The
  415. * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
  416. * and thus too short to reset the external hardware. So we use the
  417. * watchdog to reset the board.
  418. */
  419. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  420. {
  421. /* prevent triggering the watchdog */
  422. disable_interrupts ();
  423. /* make sure the watchdog is running */
  424. reset_8xx_watchdog ((immap_t *) CFG_IMMR);
  425. /* wait for watchdog reset */
  426. while (1) {};
  427. /* NOTREACHED */
  428. return 1;
  429. }
  430. #endif /* CONFIG_LWMON */
  431. /* ------------------------------------------------------------------------- */
  432. /*
  433. * Get timebase clock frequency (like cpu_clk in Hz)
  434. *
  435. * See sections 14.2 and 14.6 of the User's Manual
  436. */
  437. unsigned long get_tbclk (void)
  438. {
  439. uint immr = get_immr (0); /* Return full IMMR contents */
  440. volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
  441. ulong oscclk, factor, pll;
  442. if (immap->im_clkrst.car_sccr & SCCR_TBS) {
  443. return (gd->cpu_clk / 16);
  444. }
  445. pll = immap->im_clkrst.car_plprcr;
  446. #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
  447. /*
  448. * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
  449. * factor is calculated as follows:
  450. *
  451. * MFN
  452. * MFI + -------
  453. * MFD + 1
  454. * factor = -----------------
  455. * (PDF + 1) * 2^S
  456. *
  457. * For older chips, it's just MF field of PLPRCR plus one.
  458. */
  459. if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
  460. factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
  461. (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
  462. } else {
  463. factor = PLPRCR_val(MF)+1;
  464. }
  465. oscclk = gd->cpu_clk / factor;
  466. if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
  467. return (oscclk / 4);
  468. }
  469. return (oscclk / 16);
  470. }
  471. /* ------------------------------------------------------------------------- */
  472. #if defined(CONFIG_WATCHDOG)
  473. void watchdog_reset (void)
  474. {
  475. int re_enable = disable_interrupts ();
  476. reset_8xx_watchdog ((immap_t *) CFG_IMMR);
  477. if (re_enable)
  478. enable_interrupts ();
  479. }
  480. #endif /* CONFIG_WATCHDOG */
  481. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
  482. void reset_8xx_watchdog (volatile immap_t * immr)
  483. {
  484. # if defined(CONFIG_LWMON)
  485. /*
  486. * The LWMON board uses a MAX6301 Watchdog
  487. * with the trigger pin connected to port PA.7
  488. *
  489. * (The old board version used a MAX706TESA Watchdog, which
  490. * had to be handled exactly the same.)
  491. */
  492. # define WATCHDOG_BIT 0x0100
  493. immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
  494. immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
  495. immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
  496. immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
  497. # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
  498. /*
  499. * The KUP4 boards uses a TPS3705 Watchdog
  500. * with the trigger pin connected to port PA.5
  501. */
  502. # define WATCHDOG_BIT 0x0400
  503. immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
  504. immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
  505. immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
  506. immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
  507. # else
  508. /*
  509. * All other boards use the MPC8xx Internal Watchdog
  510. */
  511. immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
  512. immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
  513. # endif /* CONFIG_LWMON */
  514. }
  515. #endif /* CONFIG_WATCHDOG */
  516. /* ------------------------------------------------------------------------- */