mx6qsabrelite.c 12 KB

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  1. /*
  2. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/imx-regs.h>
  25. #include <asm/arch/mx6x_pins.h>
  26. #include <asm/arch/iomux-v3.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/errno.h>
  29. #include <asm/gpio.h>
  30. #include <mmc.h>
  31. #include <fsl_esdhc.h>
  32. #include <micrel.h>
  33. #include <miiphy.h>
  34. #include <netdev.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  37. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  38. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  40. PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  41. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  43. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  45. #define SPI_PAD_CTRL (PAD_CTL_HYS | \
  46. PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
  47. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  48. #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  49. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  50. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51. int dram_init(void)
  52. {
  53. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  54. return 0;
  55. }
  56. iomux_v3_cfg_t uart1_pads[] = {
  57. MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  58. MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  59. };
  60. iomux_v3_cfg_t uart2_pads[] = {
  61. MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  62. MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. };
  64. iomux_v3_cfg_t usdhc3_pads[] = {
  65. MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66. MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67. MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68. MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69. MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70. MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71. MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  72. };
  73. iomux_v3_cfg_t usdhc4_pads[] = {
  74. MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75. MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76. MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  81. };
  82. iomux_v3_cfg_t enet_pads1[] = {
  83. MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84. MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86. MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87. MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90. MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91. MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. /* pin 35 - 1 (PHY_AD2) on reset */
  93. MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  94. /* pin 32 - 1 - (MODE0) all */
  95. MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  96. /* pin 31 - 1 - (MODE1) all */
  97. MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  98. /* pin 28 - 1 - (MODE2) all */
  99. MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  100. /* pin 27 - 1 - (MODE3) all */
  101. MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  103. MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  104. /* pin 42 PHY nRST */
  105. MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  106. };
  107. iomux_v3_cfg_t enet_pads2[] = {
  108. MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  109. MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  110. MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  111. MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  112. MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  113. MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  114. };
  115. /* Button assignments for J14 */
  116. static iomux_v3_cfg_t button_pads[] = {
  117. /* Menu */
  118. MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  119. /* Back */
  120. MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  121. /* Labelled Search (mapped to Power under Android) */
  122. MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  123. /* Home */
  124. MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  125. /* Volume Down */
  126. MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  127. /* Volume Up */
  128. MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  129. };
  130. static void setup_iomux_enet(void)
  131. {
  132. gpio_direction_output(87, 0); /* GPIO 3-23 */
  133. gpio_direction_output(190, 1); /* GPIO 6-30 */
  134. gpio_direction_output(185, 1); /* GPIO 6-25 */
  135. gpio_direction_output(187, 1); /* GPIO 6-27 */
  136. gpio_direction_output(188, 1); /* GPIO 6-28*/
  137. gpio_direction_output(189, 1); /* GPIO 6-29 */
  138. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  139. gpio_direction_output(184, 1); /* GPIO 6-24 */
  140. /* Need delay 10ms according to KSZ9021 spec */
  141. udelay(1000 * 10);
  142. gpio_set_value(87, 1); /* GPIO 3-23 */
  143. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  144. }
  145. iomux_v3_cfg_t usb_pads[] = {
  146. MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  147. };
  148. static void setup_iomux_uart(void)
  149. {
  150. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  151. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  152. }
  153. #ifdef CONFIG_USB_EHCI_MX6
  154. int board_ehci_hcd_init(int port)
  155. {
  156. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  157. /* Reset USB hub */
  158. gpio_direction_output(GPIO_NUMBER(7, 12), 0);
  159. mdelay(2);
  160. gpio_set_value(GPIO_NUMBER(7, 12), 1);
  161. return 0;
  162. }
  163. #endif
  164. #ifdef CONFIG_FSL_ESDHC
  165. struct fsl_esdhc_cfg usdhc_cfg[2] = {
  166. {USDHC3_BASE_ADDR, 1},
  167. {USDHC4_BASE_ADDR, 1},
  168. };
  169. int board_mmc_getcd(struct mmc *mmc)
  170. {
  171. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  172. int ret;
  173. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  174. gpio_direction_input(192); /*GPIO7_0*/
  175. ret = !gpio_get_value(192);
  176. } else {
  177. gpio_direction_input(38); /*GPIO2_6*/
  178. ret = !gpio_get_value(38);
  179. }
  180. return ret;
  181. }
  182. int board_mmc_init(bd_t *bis)
  183. {
  184. s32 status = 0;
  185. u32 index = 0;
  186. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  187. switch (index) {
  188. case 0:
  189. imx_iomux_v3_setup_multiple_pads(
  190. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  191. break;
  192. case 1:
  193. imx_iomux_v3_setup_multiple_pads(
  194. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  195. break;
  196. default:
  197. printf("Warning: you configured more USDHC controllers"
  198. "(%d) then supported by the board (%d)\n",
  199. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  200. return status;
  201. }
  202. status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  203. }
  204. return status;
  205. }
  206. #endif
  207. u32 get_board_rev(void)
  208. {
  209. return 0x63000 ;
  210. }
  211. #ifdef CONFIG_MXC_SPI
  212. iomux_v3_cfg_t ecspi1_pads[] = {
  213. /* SS1 */
  214. MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  215. MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  216. MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  217. MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  218. };
  219. void setup_spi(void)
  220. {
  221. gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
  222. imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  223. ARRAY_SIZE(ecspi1_pads));
  224. }
  225. #endif
  226. int board_phy_config(struct phy_device *phydev)
  227. {
  228. /* min rx data delay */
  229. ksz9021_phy_extended_write(phydev,
  230. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  231. /* min tx data delay */
  232. ksz9021_phy_extended_write(phydev,
  233. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  234. /* max rx/tx clock delay, min rx/tx control */
  235. ksz9021_phy_extended_write(phydev,
  236. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  237. if (phydev->drv->config)
  238. phydev->drv->config(phydev);
  239. return 0;
  240. }
  241. int board_eth_init(bd_t *bis)
  242. {
  243. int ret;
  244. setup_iomux_enet();
  245. ret = cpu_eth_init(bis);
  246. if (ret)
  247. printf("FEC MXC: %s:failed\n", __func__);
  248. return 0;
  249. }
  250. static void setup_buttons(void)
  251. {
  252. imx_iomux_v3_setup_multiple_pads(button_pads,
  253. ARRAY_SIZE(button_pads));
  254. }
  255. #ifdef CONFIG_CMD_SATA
  256. int setup_sata(void)
  257. {
  258. struct iomuxc_base_regs *const iomuxc_regs
  259. = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
  260. int ret = enable_sata_clock();
  261. if (ret)
  262. return ret;
  263. clrsetbits_le32(&iomuxc_regs->gpr[13],
  264. IOMUXC_GPR13_SATA_MASK,
  265. IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
  266. |IOMUXC_GPR13_SATA_PHY_7_SATA2M
  267. |IOMUXC_GPR13_SATA_SPEED_3G
  268. |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
  269. |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
  270. |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
  271. |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
  272. |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
  273. |IOMUXC_GPR13_SATA_PHY_1_SLOW);
  274. return 0;
  275. }
  276. #endif
  277. int board_early_init_f(void)
  278. {
  279. setup_iomux_uart();
  280. setup_buttons();
  281. return 0;
  282. }
  283. int board_init(void)
  284. {
  285. /* address of boot parameters */
  286. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  287. #ifdef CONFIG_MXC_SPI
  288. setup_spi();
  289. #endif
  290. #ifdef CONFIG_CMD_SATA
  291. setup_sata();
  292. #endif
  293. return 0;
  294. }
  295. int checkboard(void)
  296. {
  297. puts("Board: MX6Q-Sabre Lite\n");
  298. return 0;
  299. }
  300. struct button_key {
  301. char const *name;
  302. unsigned gpnum;
  303. char ident;
  304. };
  305. static struct button_key const buttons[] = {
  306. {"back", GPIO_NUMBER(2, 2), 'B'},
  307. {"home", GPIO_NUMBER(2, 4), 'H'},
  308. {"menu", GPIO_NUMBER(2, 1), 'M'},
  309. {"search", GPIO_NUMBER(2, 3), 'S'},
  310. {"volup", GPIO_NUMBER(7, 13), 'V'},
  311. {"voldown", GPIO_NUMBER(4, 5), 'v'},
  312. };
  313. /*
  314. * generate a null-terminated string containing the buttons pressed
  315. * returns number of keys pressed
  316. */
  317. static int read_keys(char *buf)
  318. {
  319. int i, numpressed = 0;
  320. for (i = 0; i < ARRAY_SIZE(buttons); i++) {
  321. if (!gpio_get_value(buttons[i].gpnum))
  322. buf[numpressed++] = buttons[i].ident;
  323. }
  324. buf[numpressed] = '\0';
  325. return numpressed;
  326. }
  327. static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  328. {
  329. char envvalue[ARRAY_SIZE(buttons)+1];
  330. int numpressed = read_keys(envvalue);
  331. setenv("keybd", envvalue);
  332. return numpressed == 0;
  333. }
  334. U_BOOT_CMD(
  335. kbd, 1, 1, do_kbd,
  336. "Tests for keypresses, sets 'keybd' environment variable",
  337. "Returns 0 (true) to shell if key is pressed."
  338. );
  339. #ifdef CONFIG_PREBOOT
  340. static char const kbd_magic_prefix[] = "key_magic";
  341. static char const kbd_command_prefix[] = "key_cmd";
  342. static void preboot_keys(void)
  343. {
  344. int numpressed;
  345. char keypress[ARRAY_SIZE(buttons)+1];
  346. numpressed = read_keys(keypress);
  347. if (numpressed) {
  348. char *kbd_magic_keys = getenv("magic_keys");
  349. char *suffix;
  350. /*
  351. * loop over all magic keys
  352. */
  353. for (suffix = kbd_magic_keys; *suffix; ++suffix) {
  354. char *keys;
  355. char magic[sizeof(kbd_magic_prefix) + 1];
  356. sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
  357. keys = getenv(magic);
  358. if (keys) {
  359. if (!strcmp(keys, keypress))
  360. break;
  361. }
  362. }
  363. if (*suffix) {
  364. char cmd_name[sizeof(kbd_command_prefix) + 1];
  365. char *cmd;
  366. sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
  367. cmd = getenv(cmd_name);
  368. if (cmd) {
  369. setenv("preboot", cmd);
  370. return;
  371. }
  372. }
  373. }
  374. }
  375. #endif
  376. int misc_init_r(void)
  377. {
  378. #ifdef CONFIG_PREBOOT
  379. preboot_keys();
  380. #endif
  381. return 0;
  382. }