tegra20-tamonten.dtsi 10 KB

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  1. #include "tegra20.dtsi"
  2. / {
  3. model = "Avionic Design Tamonten SOM";
  4. compatible = "ad,tamonten", "nvidia,tegra20";
  5. memory {
  6. reg = <0x00000000 0x20000000>;
  7. };
  8. host1x {
  9. hdmi {
  10. vdd-supply = <&hdmi_vdd_reg>;
  11. pll-supply = <&hdmi_pll_reg>;
  12. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  13. nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
  14. };
  15. };
  16. pinmux {
  17. pinctrl-names = "default";
  18. pinctrl-0 = <&state_default>;
  19. state_default: pinmux {
  20. ata {
  21. nvidia,pins = "ata";
  22. nvidia,function = "ide";
  23. };
  24. atb {
  25. nvidia,pins = "atb", "gma", "gme";
  26. nvidia,function = "sdio4";
  27. };
  28. atc {
  29. nvidia,pins = "atc";
  30. nvidia,function = "nand";
  31. };
  32. atd {
  33. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  34. "spia", "spib", "spic";
  35. nvidia,function = "gmi";
  36. };
  37. cdev1 {
  38. nvidia,pins = "cdev1";
  39. nvidia,function = "plla_out";
  40. };
  41. cdev2 {
  42. nvidia,pins = "cdev2";
  43. nvidia,function = "pllp_out4";
  44. };
  45. crtp {
  46. nvidia,pins = "crtp";
  47. nvidia,function = "crt";
  48. };
  49. csus {
  50. nvidia,pins = "csus";
  51. nvidia,function = "vi_sensor_clk";
  52. };
  53. dap1 {
  54. nvidia,pins = "dap1";
  55. nvidia,function = "dap1";
  56. };
  57. dap2 {
  58. nvidia,pins = "dap2";
  59. nvidia,function = "dap2";
  60. };
  61. dap3 {
  62. nvidia,pins = "dap3";
  63. nvidia,function = "dap3";
  64. };
  65. dap4 {
  66. nvidia,pins = "dap4";
  67. nvidia,function = "dap4";
  68. };
  69. dta {
  70. nvidia,pins = "dta", "dtd";
  71. nvidia,function = "sdio2";
  72. };
  73. dtb {
  74. nvidia,pins = "dtb", "dtc", "dte";
  75. nvidia,function = "rsvd1";
  76. };
  77. dtf {
  78. nvidia,pins = "dtf";
  79. nvidia,function = "i2c3";
  80. };
  81. gmc {
  82. nvidia,pins = "gmc";
  83. nvidia,function = "uartd";
  84. };
  85. gpu7 {
  86. nvidia,pins = "gpu7";
  87. nvidia,function = "rtck";
  88. };
  89. gpv {
  90. nvidia,pins = "gpv", "slxa", "slxk";
  91. nvidia,function = "pcie";
  92. };
  93. hdint {
  94. nvidia,pins = "hdint";
  95. nvidia,function = "hdmi";
  96. };
  97. i2cp {
  98. nvidia,pins = "i2cp";
  99. nvidia,function = "i2cp";
  100. };
  101. irrx {
  102. nvidia,pins = "irrx", "irtx";
  103. nvidia,function = "uarta";
  104. };
  105. kbca {
  106. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  107. "kbce", "kbcf";
  108. nvidia,function = "kbc";
  109. };
  110. lcsn {
  111. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  112. "ld3", "ld4", "ld5", "ld6", "ld7",
  113. "ld8", "ld9", "ld10", "ld11", "ld12",
  114. "ld13", "ld14", "ld15", "ld16", "ld17",
  115. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  116. "lhs", "lm0", "lm1", "lpp", "lpw0",
  117. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  118. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  119. "lvs";
  120. nvidia,function = "displaya";
  121. };
  122. owc {
  123. nvidia,pins = "owc", "spdi", "spdo", "uac";
  124. nvidia,function = "rsvd2";
  125. };
  126. pmc {
  127. nvidia,pins = "pmc";
  128. nvidia,function = "pwr_on";
  129. };
  130. rm {
  131. nvidia,pins = "rm";
  132. nvidia,function = "i2c1";
  133. };
  134. sdb {
  135. nvidia,pins = "sdb", "sdc", "sdd";
  136. nvidia,function = "pwm";
  137. };
  138. sdio1 {
  139. nvidia,pins = "sdio1";
  140. nvidia,function = "sdio1";
  141. };
  142. slxc {
  143. nvidia,pins = "slxc", "slxd";
  144. nvidia,function = "spdif";
  145. };
  146. spid {
  147. nvidia,pins = "spid", "spie", "spif";
  148. nvidia,function = "spi1";
  149. };
  150. spig {
  151. nvidia,pins = "spig", "spih";
  152. nvidia,function = "spi2_alt";
  153. };
  154. uaa {
  155. nvidia,pins = "uaa", "uab", "uda";
  156. nvidia,function = "ulpi";
  157. };
  158. uad {
  159. nvidia,pins = "uad";
  160. nvidia,function = "irda";
  161. };
  162. uca {
  163. nvidia,pins = "uca", "ucb";
  164. nvidia,function = "uartc";
  165. };
  166. conf_ata {
  167. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  168. "cdev1", "cdev2", "dap1", "dtb", "gma",
  169. "gmb", "gmc", "gmd", "gme", "gpu7",
  170. "gpv", "i2cp", "pta", "rm", "slxa",
  171. "slxk", "spia", "spib", "uac";
  172. nvidia,pull = <0>;
  173. nvidia,tristate = <0>;
  174. };
  175. conf_ck32 {
  176. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  177. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  178. nvidia,pull = <0>;
  179. };
  180. conf_csus {
  181. nvidia,pins = "csus", "spid", "spif";
  182. nvidia,pull = <1>;
  183. nvidia,tristate = <1>;
  184. };
  185. conf_crtp {
  186. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  187. "dtc", "dte", "dtf", "gpu", "sdio1",
  188. "slxc", "slxd", "spdi", "spdo", "spig",
  189. "uda";
  190. nvidia,pull = <0>;
  191. nvidia,tristate = <1>;
  192. };
  193. conf_ddc {
  194. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  195. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  196. "sdc";
  197. nvidia,pull = <2>;
  198. nvidia,tristate = <0>;
  199. };
  200. conf_hdint {
  201. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  202. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  203. "lvp0", "owc", "sdb";
  204. nvidia,tristate = <1>;
  205. };
  206. conf_irrx {
  207. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  208. "spie", "spih", "uaa", "uab", "uad",
  209. "uca", "ucb";
  210. nvidia,pull = <2>;
  211. nvidia,tristate = <1>;
  212. };
  213. conf_lc {
  214. nvidia,pins = "lc", "ls";
  215. nvidia,pull = <2>;
  216. };
  217. conf_ld0 {
  218. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  219. "ld5", "ld6", "ld7", "ld8", "ld9",
  220. "ld10", "ld11", "ld12", "ld13", "ld14",
  221. "ld15", "ld16", "ld17", "ldi", "lhp0",
  222. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  223. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  224. "lvs", "pmc";
  225. nvidia,tristate = <0>;
  226. };
  227. conf_ld17_0 {
  228. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  229. "ld23_22";
  230. nvidia,pull = <1>;
  231. };
  232. };
  233. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  234. ddc {
  235. nvidia,pins = "ddc";
  236. nvidia,function = "i2c2";
  237. };
  238. pta {
  239. nvidia,pins = "pta";
  240. nvidia,function = "rsvd4";
  241. };
  242. };
  243. state_i2cmux_pta: pinmux_i2cmux_pta {
  244. ddc {
  245. nvidia,pins = "ddc";
  246. nvidia,function = "rsvd4";
  247. };
  248. pta {
  249. nvidia,pins = "pta";
  250. nvidia,function = "i2c2";
  251. };
  252. };
  253. state_i2cmux_idle: pinmux_i2cmux_idle {
  254. ddc {
  255. nvidia,pins = "ddc";
  256. nvidia,function = "rsvd4";
  257. };
  258. pta {
  259. nvidia,pins = "pta";
  260. nvidia,function = "rsvd4";
  261. };
  262. };
  263. };
  264. i2s@70002800 {
  265. status = "okay";
  266. };
  267. serial@70006300 {
  268. status = "okay";
  269. };
  270. nand-controller@70008000 {
  271. nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
  272. nvidia,width = <8>;
  273. nvidia,timing = <26 100 20 80 20 10 12 10 70>;
  274. nand@0 {
  275. reg = <0>;
  276. compatible = "hynix,hy27uf4g2b", "nand-flash";
  277. };
  278. };
  279. i2c@7000c000 {
  280. clock-frequency = <400000>;
  281. status = "okay";
  282. };
  283. i2c@7000c400 {
  284. clock-frequency = <100000>;
  285. status = "okay";
  286. };
  287. i2cmux {
  288. compatible = "i2c-mux-pinctrl";
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. i2c-parent = <&{/i2c@7000c400}>;
  292. pinctrl-names = "ddc", "pta", "idle";
  293. pinctrl-0 = <&state_i2cmux_ddc>;
  294. pinctrl-1 = <&state_i2cmux_pta>;
  295. pinctrl-2 = <&state_i2cmux_idle>;
  296. hdmi_ddc: i2c@0 {
  297. reg = <0>;
  298. #address-cells = <1>;
  299. #size-cells = <0>;
  300. };
  301. i2c@1 {
  302. reg = <1>;
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. };
  306. };
  307. i2c@7000d000 {
  308. clock-frequency = <400000>;
  309. status = "okay";
  310. pmic: tps6586x@34 {
  311. compatible = "ti,tps6586x";
  312. reg = <0x34>;
  313. interrupts = <0 86 0x4>;
  314. ti,system-power-controller;
  315. #gpio-cells = <2>;
  316. gpio-controller;
  317. sys-supply = <&vdd_5v0_reg>;
  318. vin-sm0-supply = <&sys_reg>;
  319. vin-sm1-supply = <&sys_reg>;
  320. vin-sm2-supply = <&sys_reg>;
  321. vinldo01-supply = <&sm2_reg>;
  322. vinldo23-supply = <&sm2_reg>;
  323. vinldo4-supply = <&sm2_reg>;
  324. vinldo678-supply = <&sm2_reg>;
  325. vinldo9-supply = <&sm2_reg>;
  326. regulators {
  327. sys_reg: sys {
  328. regulator-name = "vdd_sys";
  329. regulator-always-on;
  330. };
  331. sm0 {
  332. regulator-name = "vdd_sys_sm0,vdd_core";
  333. regulator-min-microvolt = <1200000>;
  334. regulator-max-microvolt = <1200000>;
  335. regulator-always-on;
  336. };
  337. sm1 {
  338. regulator-name = "vdd_sys_sm1,vdd_cpu";
  339. regulator-min-microvolt = <1000000>;
  340. regulator-max-microvolt = <1000000>;
  341. regulator-always-on;
  342. };
  343. sm2_reg: sm2 {
  344. regulator-name = "vdd_sys_sm2,vin_ldo*";
  345. regulator-min-microvolt = <3700000>;
  346. regulator-max-microvolt = <3700000>;
  347. regulator-always-on;
  348. };
  349. ldo0 {
  350. regulator-name = "vdd_ldo0,vddio_pex_clk";
  351. regulator-min-microvolt = <3300000>;
  352. regulator-max-microvolt = <3300000>;
  353. };
  354. ldo1 {
  355. regulator-name = "vdd_ldo1,avdd_pll*";
  356. regulator-min-microvolt = <1100000>;
  357. regulator-max-microvolt = <1100000>;
  358. regulator-always-on;
  359. };
  360. ldo2 {
  361. regulator-name = "vdd_ldo2,vdd_rtc";
  362. regulator-min-microvolt = <1200000>;
  363. regulator-max-microvolt = <1200000>;
  364. };
  365. ldo3 {
  366. regulator-name = "vdd_ldo3,avdd_usb*";
  367. regulator-min-microvolt = <3300000>;
  368. regulator-max-microvolt = <3300000>;
  369. regulator-always-on;
  370. };
  371. ldo4 {
  372. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  373. regulator-min-microvolt = <1800000>;
  374. regulator-max-microvolt = <1800000>;
  375. regulator-always-on;
  376. };
  377. ldo5 {
  378. regulator-name = "vdd_ldo5,vcore_mmc";
  379. regulator-min-microvolt = <2850000>;
  380. regulator-max-microvolt = <2850000>;
  381. };
  382. ldo6 {
  383. regulator-name = "vdd_ldo6,avdd_vdac";
  384. /*
  385. * According to the Tegra 2 Automotive
  386. * DataSheet, a typical value for this
  387. * would be 2.8V, but the PMIC only
  388. * supports 2.85V.
  389. */
  390. regulator-min-microvolt = <2850000>;
  391. regulator-max-microvolt = <2850000>;
  392. };
  393. hdmi_vdd_reg: ldo7 {
  394. regulator-name = "vdd_ldo7,avdd_hdmi";
  395. regulator-min-microvolt = <3300000>;
  396. regulator-max-microvolt = <3300000>;
  397. };
  398. hdmi_pll_reg: ldo8 {
  399. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  400. regulator-min-microvolt = <1800000>;
  401. regulator-max-microvolt = <1800000>;
  402. };
  403. ldo9 {
  404. regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
  405. /*
  406. * According to the Tegra 2 Automotive
  407. * DataSheet, a typical value for this
  408. * would be 2.8V, but the PMIC only
  409. * supports 2.85V.
  410. */
  411. regulator-min-microvolt = <2850000>;
  412. regulator-max-microvolt = <2850000>;
  413. regulator-always-on;
  414. };
  415. ldo_rtc {
  416. regulator-name = "vdd_rtc_out";
  417. regulator-min-microvolt = <3300000>;
  418. regulator-max-microvolt = <3300000>;
  419. regulator-always-on;
  420. };
  421. };
  422. };
  423. temperature-sensor@4c {
  424. compatible = "onnn,nct1008";
  425. reg = <0x4c>;
  426. };
  427. };
  428. pmc {
  429. nvidia,invert-interrupt;
  430. };
  431. usb@c5008000 {
  432. status = "okay";
  433. };
  434. sdhci@c8000600 {
  435. cd-gpios = <&gpio 58 1>; /* gpio PH2 */
  436. wp-gpios = <&gpio 59 0>; /* gpio PH3 */
  437. bus-width = <4>;
  438. status = "okay";
  439. };
  440. regulators {
  441. compatible = "simple-bus";
  442. #address-cells = <1>;
  443. #size-cells = <0>;
  444. vdd_5v0_reg: regulator@0 {
  445. compatible = "regulator-fixed";
  446. reg = <0>;
  447. regulator-name = "vdd_5v0";
  448. regulator-min-microvolt = <5000000>;
  449. regulator-max-microvolt = <5000000>;
  450. regulator-always-on;
  451. };
  452. };
  453. };