musb_hcd.c 30 KB

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  1. /*
  2. * Mentor USB OTG Core host controller driver.
  3. *
  4. * Copyright (c) 2008 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. *
  21. * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
  22. */
  23. #include <common.h>
  24. #include "musb_hcd.h"
  25. /* MSC control transfers */
  26. #define USB_MSC_BBB_RESET 0xFF
  27. #define USB_MSC_BBB_GET_MAX_LUN 0xFE
  28. /* Endpoint configuration information */
  29. static struct musb_epinfo epinfo[3] = {
  30. {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
  31. {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
  32. {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
  33. };
  34. /* --- Virtual Root Hub ---------------------------------------------------- */
  35. #ifdef MUSB_NO_MULTIPOINT
  36. static int rh_devnum;
  37. static u32 port_status;
  38. /* Device descriptor */
  39. static u8 root_hub_dev_des[] = {
  40. 0x12, /* __u8 bLength; */
  41. 0x01, /* __u8 bDescriptorType; Device */
  42. 0x00, /* __u16 bcdUSB; v1.1 */
  43. 0x02,
  44. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  45. 0x00, /* __u8 bDeviceSubClass; */
  46. 0x00, /* __u8 bDeviceProtocol; */
  47. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  48. 0x00, /* __u16 idVendor; */
  49. 0x00,
  50. 0x00, /* __u16 idProduct; */
  51. 0x00,
  52. 0x00, /* __u16 bcdDevice; */
  53. 0x00,
  54. 0x00, /* __u8 iManufacturer; */
  55. 0x01, /* __u8 iProduct; */
  56. 0x00, /* __u8 iSerialNumber; */
  57. 0x01 /* __u8 bNumConfigurations; */
  58. };
  59. /* Configuration descriptor */
  60. static u8 root_hub_config_des[] = {
  61. 0x09, /* __u8 bLength; */
  62. 0x02, /* __u8 bDescriptorType; Configuration */
  63. 0x19, /* __u16 wTotalLength; */
  64. 0x00,
  65. 0x01, /* __u8 bNumInterfaces; */
  66. 0x01, /* __u8 bConfigurationValue; */
  67. 0x00, /* __u8 iConfiguration; */
  68. 0x40, /* __u8 bmAttributes;
  69. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  70. 0x00, /* __u8 MaxPower; */
  71. /* interface */
  72. 0x09, /* __u8 if_bLength; */
  73. 0x04, /* __u8 if_bDescriptorType; Interface */
  74. 0x00, /* __u8 if_bInterfaceNumber; */
  75. 0x00, /* __u8 if_bAlternateSetting; */
  76. 0x01, /* __u8 if_bNumEndpoints; */
  77. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  78. 0x00, /* __u8 if_bInterfaceSubClass; */
  79. 0x00, /* __u8 if_bInterfaceProtocol; */
  80. 0x00, /* __u8 if_iInterface; */
  81. /* endpoint */
  82. 0x07, /* __u8 ep_bLength; */
  83. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  84. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  85. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  86. 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  87. 0x02,
  88. 0xff /* __u8 ep_bInterval; 255 ms */
  89. };
  90. static unsigned char root_hub_str_index0[] = {
  91. 0x04, /* __u8 bLength; */
  92. 0x03, /* __u8 bDescriptorType; String-descriptor */
  93. 0x09, /* __u8 lang ID */
  94. 0x04, /* __u8 lang ID */
  95. };
  96. static unsigned char root_hub_str_index1[] = {
  97. 0x1c, /* __u8 bLength; */
  98. 0x03, /* __u8 bDescriptorType; String-descriptor */
  99. 'M', /* __u8 Unicode */
  100. 0, /* __u8 Unicode */
  101. 'U', /* __u8 Unicode */
  102. 0, /* __u8 Unicode */
  103. 'S', /* __u8 Unicode */
  104. 0, /* __u8 Unicode */
  105. 'B', /* __u8 Unicode */
  106. 0, /* __u8 Unicode */
  107. ' ', /* __u8 Unicode */
  108. 0, /* __u8 Unicode */
  109. 'R', /* __u8 Unicode */
  110. 0, /* __u8 Unicode */
  111. 'o', /* __u8 Unicode */
  112. 0, /* __u8 Unicode */
  113. 'o', /* __u8 Unicode */
  114. 0, /* __u8 Unicode */
  115. 't', /* __u8 Unicode */
  116. 0, /* __u8 Unicode */
  117. ' ', /* __u8 Unicode */
  118. 0, /* __u8 Unicode */
  119. 'H', /* __u8 Unicode */
  120. 0, /* __u8 Unicode */
  121. 'u', /* __u8 Unicode */
  122. 0, /* __u8 Unicode */
  123. 'b', /* __u8 Unicode */
  124. 0, /* __u8 Unicode */
  125. };
  126. #endif
  127. /*
  128. * This function writes the data toggle value.
  129. */
  130. static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
  131. {
  132. u16 toggle = usb_gettoggle(dev, ep, dir_out);
  133. u16 csr;
  134. if (dir_out) {
  135. if (!toggle)
  136. writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
  137. else {
  138. csr = readw(&musbr->txcsr);
  139. csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
  140. writew(csr, &musbr->txcsr);
  141. csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
  142. writew(csr, &musbr->txcsr);
  143. }
  144. } else {
  145. if (!toggle)
  146. writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
  147. else {
  148. csr = readw(&musbr->rxcsr);
  149. csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
  150. writew(csr, &musbr->rxcsr);
  151. csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
  152. writew(csr, &musbr->rxcsr);
  153. }
  154. }
  155. }
  156. /*
  157. * This function checks if RxStall has occured on the endpoint. If a RxStall
  158. * has occured, the RxStall is cleared and 1 is returned. If RxStall has
  159. * not occured, 0 is returned.
  160. */
  161. static u8 check_stall(u8 ep, u8 dir_out)
  162. {
  163. u16 csr;
  164. /* For endpoint 0 */
  165. if (!ep) {
  166. csr = readw(&musbr->txcsr);
  167. if (csr & MUSB_CSR0_H_RXSTALL) {
  168. csr &= ~MUSB_CSR0_H_RXSTALL;
  169. writew(csr, &musbr->txcsr);
  170. return 1;
  171. }
  172. } else { /* For non-ep0 */
  173. if (dir_out) { /* is it tx ep */
  174. csr = readw(&musbr->txcsr);
  175. if (csr & MUSB_TXCSR_H_RXSTALL) {
  176. csr &= ~MUSB_TXCSR_H_RXSTALL;
  177. writew(csr, &musbr->txcsr);
  178. return 1;
  179. }
  180. } else { /* is it rx ep */
  181. csr = readw(&musbr->rxcsr);
  182. if (csr & MUSB_RXCSR_H_RXSTALL) {
  183. csr &= ~MUSB_RXCSR_H_RXSTALL;
  184. writew(csr, &musbr->rxcsr);
  185. return 1;
  186. }
  187. }
  188. }
  189. return 0;
  190. }
  191. /*
  192. * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
  193. * error and -2 for stall.
  194. */
  195. static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
  196. {
  197. u16 csr;
  198. int result = 1;
  199. int timeout = CONFIG_MUSB_TIMEOUT;
  200. while (result > 0) {
  201. csr = readw(&musbr->txcsr);
  202. if (csr & MUSB_CSR0_H_ERROR) {
  203. csr &= ~MUSB_CSR0_H_ERROR;
  204. writew(csr, &musbr->txcsr);
  205. dev->status = USB_ST_CRC_ERR;
  206. result = -1;
  207. break;
  208. }
  209. switch (bit_mask) {
  210. case MUSB_CSR0_TXPKTRDY:
  211. if (!(csr & MUSB_CSR0_TXPKTRDY)) {
  212. if (check_stall(MUSB_CONTROL_EP, 0)) {
  213. dev->status = USB_ST_STALLED;
  214. result = -2;
  215. } else
  216. result = 0;
  217. }
  218. break;
  219. case MUSB_CSR0_RXPKTRDY:
  220. if (check_stall(MUSB_CONTROL_EP, 0)) {
  221. dev->status = USB_ST_STALLED;
  222. result = -2;
  223. } else
  224. if (csr & MUSB_CSR0_RXPKTRDY)
  225. result = 0;
  226. break;
  227. case MUSB_CSR0_H_REQPKT:
  228. if (!(csr & MUSB_CSR0_H_REQPKT)) {
  229. if (check_stall(MUSB_CONTROL_EP, 0)) {
  230. dev->status = USB_ST_STALLED;
  231. result = -2;
  232. } else
  233. result = 0;
  234. }
  235. break;
  236. }
  237. /* Check the timeout */
  238. if (--timeout)
  239. udelay(1);
  240. else {
  241. dev->status = USB_ST_CRC_ERR;
  242. result = -1;
  243. break;
  244. }
  245. }
  246. return result;
  247. }
  248. /*
  249. * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
  250. */
  251. static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
  252. {
  253. u16 csr;
  254. int timeout = CONFIG_MUSB_TIMEOUT;
  255. do {
  256. if (check_stall(ep, 1)) {
  257. dev->status = USB_ST_STALLED;
  258. return 0;
  259. }
  260. csr = readw(&musbr->txcsr);
  261. if (csr & MUSB_TXCSR_H_ERROR) {
  262. dev->status = USB_ST_CRC_ERR;
  263. return 0;
  264. }
  265. /* Check the timeout */
  266. if (--timeout)
  267. udelay(1);
  268. else {
  269. dev->status = USB_ST_CRC_ERR;
  270. return -1;
  271. }
  272. } while (csr & MUSB_TXCSR_TXPKTRDY);
  273. return 1;
  274. }
  275. /*
  276. * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
  277. */
  278. static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
  279. {
  280. u16 csr;
  281. int timeout = CONFIG_MUSB_TIMEOUT;
  282. do {
  283. if (check_stall(ep, 0)) {
  284. dev->status = USB_ST_STALLED;
  285. return 0;
  286. }
  287. csr = readw(&musbr->rxcsr);
  288. if (csr & MUSB_RXCSR_H_ERROR) {
  289. dev->status = USB_ST_CRC_ERR;
  290. return 0;
  291. }
  292. /* Check the timeout */
  293. if (--timeout)
  294. udelay(1);
  295. else {
  296. dev->status = USB_ST_CRC_ERR;
  297. return -1;
  298. }
  299. } while (!(csr & MUSB_RXCSR_RXPKTRDY));
  300. return 1;
  301. }
  302. /*
  303. * This function performs the setup phase of the control transfer
  304. */
  305. static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
  306. {
  307. int result;
  308. u16 csr;
  309. /* write the control request to ep0 fifo */
  310. write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
  311. /* enable transfer of setup packet */
  312. csr = readw(&musbr->txcsr);
  313. csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
  314. writew(csr, &musbr->txcsr);
  315. /* wait until the setup packet is transmitted */
  316. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  317. dev->act_len = 0;
  318. return result;
  319. }
  320. /*
  321. * This function handles the control transfer in data phase
  322. */
  323. static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
  324. {
  325. u16 csr;
  326. u32 rxlen = 0;
  327. u32 nextlen = 0;
  328. u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
  329. u8 *rxbuff = (u8 *)buffer;
  330. u8 rxedlength;
  331. int result;
  332. while (rxlen < len) {
  333. /* Determine the next read length */
  334. nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
  335. /* Set the ReqPkt bit */
  336. csr = readw(&musbr->txcsr);
  337. writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
  338. result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
  339. if (result < 0)
  340. return result;
  341. /* Actual number of bytes received by usb */
  342. rxedlength = readb(&musbr->rxcount);
  343. /* Read the data from the RxFIFO */
  344. read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
  345. /* Clear the RxPktRdy Bit */
  346. csr = readw(&musbr->txcsr);
  347. csr &= ~MUSB_CSR0_RXPKTRDY;
  348. writew(csr, &musbr->txcsr);
  349. /* short packet? */
  350. if (rxedlength != nextlen) {
  351. dev->act_len += rxedlength;
  352. break;
  353. }
  354. rxlen += nextlen;
  355. dev->act_len = rxlen;
  356. }
  357. return 0;
  358. }
  359. /*
  360. * This function handles the control transfer out data phase
  361. */
  362. static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
  363. {
  364. u16 csr;
  365. u32 txlen = 0;
  366. u32 nextlen = 0;
  367. u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
  368. u8 *txbuff = (u8 *)buffer;
  369. int result = 0;
  370. while (txlen < len) {
  371. /* Determine the next write length */
  372. nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
  373. /* Load the data to send in FIFO */
  374. write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
  375. /* Set TXPKTRDY bit */
  376. csr = readw(&musbr->txcsr);
  377. writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY,
  378. &musbr->txcsr);
  379. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  380. if (result < 0)
  381. break;
  382. txlen += nextlen;
  383. dev->act_len = txlen;
  384. }
  385. return result;
  386. }
  387. /*
  388. * This function handles the control transfer out status phase
  389. */
  390. static int ctrlreq_out_status_phase(struct usb_device *dev)
  391. {
  392. u16 csr;
  393. int result;
  394. /* Set the StatusPkt bit */
  395. csr = readw(&musbr->txcsr);
  396. csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY |
  397. MUSB_CSR0_H_STATUSPKT);
  398. writew(csr, &musbr->txcsr);
  399. /* Wait until TXPKTRDY bit is cleared */
  400. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  401. return result;
  402. }
  403. /*
  404. * This function handles the control transfer in status phase
  405. */
  406. static int ctrlreq_in_status_phase(struct usb_device *dev)
  407. {
  408. u16 csr;
  409. int result;
  410. /* Set the StatusPkt bit and ReqPkt bit */
  411. csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
  412. writew(csr, &musbr->txcsr);
  413. result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
  414. /* clear StatusPkt bit and RxPktRdy bit */
  415. csr = readw(&musbr->txcsr);
  416. csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
  417. writew(csr, &musbr->txcsr);
  418. return result;
  419. }
  420. /*
  421. * determines the speed of the device (High/Full/Slow)
  422. */
  423. static u8 get_dev_speed(struct usb_device *dev)
  424. {
  425. return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
  426. ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
  427. MUSB_TYPE_SPEED_FULL);
  428. }
  429. /*
  430. * configure the hub address and the port address.
  431. */
  432. static void config_hub_port(struct usb_device *dev, u8 ep)
  433. {
  434. u8 chid;
  435. u8 hub;
  436. /* Find out the nearest parent which is high speed */
  437. while (dev->parent->parent != NULL)
  438. if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
  439. dev = dev->parent;
  440. else
  441. break;
  442. /* determine the port address at that hub */
  443. hub = dev->parent->devnum;
  444. for (chid = 0; chid < USB_MAXCHILDREN; chid++)
  445. if (dev->parent->children[chid] == dev)
  446. break;
  447. #ifndef MUSB_NO_MULTIPOINT
  448. /* configure the hub address and the port address */
  449. writeb(hub, &musbr->tar[ep].txhubaddr);
  450. writeb((chid + 1), &musbr->tar[ep].txhubport);
  451. writeb(hub, &musbr->tar[ep].rxhubaddr);
  452. writeb((chid + 1), &musbr->tar[ep].rxhubport);
  453. #endif
  454. }
  455. #ifdef MUSB_NO_MULTIPOINT
  456. static void musb_port_reset(int do_reset)
  457. {
  458. u8 power = readb(&musbr->power);
  459. if (do_reset) {
  460. power &= 0xf0;
  461. writeb(power | MUSB_POWER_RESET, &musbr->power);
  462. port_status |= USB_PORT_STAT_RESET;
  463. port_status &= ~USB_PORT_STAT_ENABLE;
  464. udelay(30000);
  465. } else {
  466. writeb(power & ~MUSB_POWER_RESET, &musbr->power);
  467. power = readb(&musbr->power);
  468. if (power & MUSB_POWER_HSMODE)
  469. port_status |= USB_PORT_STAT_HIGH_SPEED;
  470. port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
  471. port_status |= USB_PORT_STAT_ENABLE
  472. | (USB_PORT_STAT_C_RESET << 16)
  473. | (USB_PORT_STAT_C_ENABLE << 16);
  474. }
  475. }
  476. /*
  477. * root hub control
  478. */
  479. static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  480. void *buffer, int transfer_len,
  481. struct devrequest *cmd)
  482. {
  483. int leni = transfer_len;
  484. int len = 0;
  485. int stat = 0;
  486. u32 datab[4];
  487. u8 *data_buf = (u8 *) datab;
  488. u16 bmRType_bReq;
  489. u16 wValue;
  490. u16 wIndex;
  491. u16 wLength;
  492. u16 int_usb;
  493. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  494. debug("Root-Hub submit IRQ: NOT implemented\n");
  495. return 0;
  496. }
  497. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  498. wValue = swap_16(cmd->value);
  499. wIndex = swap_16(cmd->index);
  500. wLength = swap_16(cmd->length);
  501. debug("--- HUB ----------------------------------------\n");
  502. debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
  503. bmRType_bReq, wValue, wIndex, wLength);
  504. debug("------------------------------------------------\n");
  505. switch (bmRType_bReq) {
  506. case RH_GET_STATUS:
  507. debug("RH_GET_STATUS\n");
  508. *(__u16 *) data_buf = swap_16(1);
  509. len = 2;
  510. break;
  511. case RH_GET_STATUS | RH_INTERFACE:
  512. debug("RH_GET_STATUS | RH_INTERFACE\n");
  513. *(__u16 *) data_buf = swap_16(0);
  514. len = 2;
  515. break;
  516. case RH_GET_STATUS | RH_ENDPOINT:
  517. debug("RH_GET_STATUS | RH_ENDPOINT\n");
  518. *(__u16 *) data_buf = swap_16(0);
  519. len = 2;
  520. break;
  521. case RH_GET_STATUS | RH_CLASS:
  522. debug("RH_GET_STATUS | RH_CLASS\n");
  523. *(__u32 *) data_buf = swap_32(0);
  524. len = 4;
  525. break;
  526. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  527. debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
  528. int_usb = readw(&musbr->intrusb);
  529. if (int_usb & MUSB_INTR_CONNECT) {
  530. port_status |= USB_PORT_STAT_CONNECTION
  531. | (USB_PORT_STAT_C_CONNECTION << 16);
  532. port_status |= USB_PORT_STAT_HIGH_SPEED
  533. | USB_PORT_STAT_ENABLE;
  534. }
  535. if (port_status & USB_PORT_STAT_RESET)
  536. musb_port_reset(0);
  537. *(__u32 *) data_buf = swap_32(port_status);
  538. len = 4;
  539. break;
  540. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  541. debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
  542. switch (wValue) {
  543. case RH_ENDPOINT_STALL:
  544. debug("C_HUB_ENDPOINT_STALL\n");
  545. len = 0;
  546. break;
  547. }
  548. port_status &= ~(1 << wValue);
  549. break;
  550. case RH_CLEAR_FEATURE | RH_CLASS:
  551. debug("RH_CLEAR_FEATURE | RH_CLASS\n");
  552. switch (wValue) {
  553. case RH_C_HUB_LOCAL_POWER:
  554. debug("C_HUB_LOCAL_POWER\n");
  555. len = 0;
  556. break;
  557. case RH_C_HUB_OVER_CURRENT:
  558. debug("C_HUB_OVER_CURRENT\n");
  559. len = 0;
  560. break;
  561. }
  562. port_status &= ~(1 << wValue);
  563. break;
  564. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  565. debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
  566. switch (wValue) {
  567. case RH_PORT_ENABLE:
  568. len = 0;
  569. break;
  570. case RH_PORT_SUSPEND:
  571. len = 0;
  572. break;
  573. case RH_PORT_POWER:
  574. len = 0;
  575. break;
  576. case RH_C_PORT_CONNECTION:
  577. len = 0;
  578. break;
  579. case RH_C_PORT_ENABLE:
  580. len = 0;
  581. break;
  582. case RH_C_PORT_SUSPEND:
  583. len = 0;
  584. break;
  585. case RH_C_PORT_OVER_CURRENT:
  586. len = 0;
  587. break;
  588. case RH_C_PORT_RESET:
  589. len = 0;
  590. break;
  591. default:
  592. debug("invalid wValue\n");
  593. stat = USB_ST_STALLED;
  594. }
  595. port_status &= ~(1 << wValue);
  596. break;
  597. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  598. debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
  599. switch (wValue) {
  600. case RH_PORT_SUSPEND:
  601. len = 0;
  602. break;
  603. case RH_PORT_RESET:
  604. musb_port_reset(1);
  605. len = 0;
  606. break;
  607. case RH_PORT_POWER:
  608. len = 0;
  609. break;
  610. case RH_PORT_ENABLE:
  611. len = 0;
  612. break;
  613. default:
  614. debug("invalid wValue\n");
  615. stat = USB_ST_STALLED;
  616. }
  617. port_status |= 1 << wValue;
  618. break;
  619. case RH_SET_ADDRESS:
  620. debug("RH_SET_ADDRESS\n");
  621. rh_devnum = wValue;
  622. len = 0;
  623. break;
  624. case RH_GET_DESCRIPTOR:
  625. debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
  626. switch (wValue) {
  627. case (USB_DT_DEVICE << 8): /* device descriptor */
  628. len = min_t(unsigned int,
  629. leni, min_t(unsigned int,
  630. sizeof(root_hub_dev_des),
  631. wLength));
  632. data_buf = root_hub_dev_des;
  633. break;
  634. case (USB_DT_CONFIG << 8): /* configuration descriptor */
  635. len = min_t(unsigned int,
  636. leni, min_t(unsigned int,
  637. sizeof(root_hub_config_des),
  638. wLength));
  639. data_buf = root_hub_config_des;
  640. break;
  641. case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
  642. len = min_t(unsigned int,
  643. leni, min_t(unsigned int,
  644. sizeof(root_hub_str_index0),
  645. wLength));
  646. data_buf = root_hub_str_index0;
  647. break;
  648. case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
  649. len = min_t(unsigned int,
  650. leni, min_t(unsigned int,
  651. sizeof(root_hub_str_index1),
  652. wLength));
  653. data_buf = root_hub_str_index1;
  654. break;
  655. default:
  656. debug("invalid wValue\n");
  657. stat = USB_ST_STALLED;
  658. }
  659. break;
  660. case RH_GET_DESCRIPTOR | RH_CLASS:
  661. debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
  662. data_buf[0] = 0x09; /* min length; */
  663. data_buf[1] = 0x29;
  664. data_buf[2] = 0x1; /* 1 port */
  665. data_buf[3] = 0x01; /* per-port power switching */
  666. data_buf[3] |= 0x10; /* no overcurrent reporting */
  667. /* Corresponds to data_buf[4-7] */
  668. data_buf[4] = 0;
  669. data_buf[5] = 5;
  670. data_buf[6] = 0;
  671. data_buf[7] = 0x02;
  672. data_buf[8] = 0xff;
  673. len = min_t(unsigned int, leni,
  674. min_t(unsigned int, data_buf[0], wLength));
  675. break;
  676. case RH_GET_CONFIGURATION:
  677. debug("RH_GET_CONFIGURATION\n");
  678. *(__u8 *) data_buf = 0x01;
  679. len = 1;
  680. break;
  681. case RH_SET_CONFIGURATION:
  682. debug("RH_SET_CONFIGURATION\n");
  683. len = 0;
  684. break;
  685. default:
  686. debug("*** *** *** unsupported root hub command *** *** ***\n");
  687. stat = USB_ST_STALLED;
  688. }
  689. len = min_t(int, len, leni);
  690. if (buffer != data_buf)
  691. memcpy(buffer, data_buf, len);
  692. dev->act_len = len;
  693. dev->status = stat;
  694. debug("dev act_len %d, status %d\n", dev->act_len, dev->status);
  695. return stat;
  696. }
  697. static void musb_rh_init(void)
  698. {
  699. rh_devnum = 0;
  700. port_status = 0;
  701. }
  702. #else
  703. static void musb_rh_init(void) {}
  704. #endif
  705. /*
  706. * do a control transfer
  707. */
  708. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  709. int len, struct devrequest *setup)
  710. {
  711. int devnum = usb_pipedevice(pipe);
  712. u16 csr;
  713. u8 devspeed;
  714. #ifdef MUSB_NO_MULTIPOINT
  715. /* Control message is for the HUB? */
  716. if (devnum == rh_devnum)
  717. return musb_submit_rh_msg(dev, pipe, buffer, len, setup);
  718. #endif
  719. /* select control endpoint */
  720. writeb(MUSB_CONTROL_EP, &musbr->index);
  721. csr = readw(&musbr->txcsr);
  722. #ifndef MUSB_NO_MULTIPOINT
  723. /* target addr and (for multipoint) hub addr/port */
  724. writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
  725. writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
  726. #endif
  727. /* configure the hub address and the port number as required */
  728. devspeed = get_dev_speed(dev);
  729. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  730. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  731. config_hub_port(dev, MUSB_CONTROL_EP);
  732. writeb(devspeed << 6, &musbr->txtype);
  733. } else {
  734. writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
  735. #ifndef MUSB_NO_MULTIPOINT
  736. writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
  737. writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
  738. writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
  739. writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
  740. #endif
  741. }
  742. /* Control transfer setup phase */
  743. if (ctrlreq_setup_phase(dev, setup) < 0)
  744. return 0;
  745. switch (setup->request) {
  746. case USB_REQ_GET_DESCRIPTOR:
  747. case USB_REQ_GET_CONFIGURATION:
  748. case USB_REQ_GET_INTERFACE:
  749. case USB_REQ_GET_STATUS:
  750. case USB_MSC_BBB_GET_MAX_LUN:
  751. /* control transfer in-data-phase */
  752. if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
  753. return 0;
  754. /* control transfer out-status-phase */
  755. if (ctrlreq_out_status_phase(dev) < 0)
  756. return 0;
  757. break;
  758. case USB_REQ_SET_ADDRESS:
  759. case USB_REQ_SET_CONFIGURATION:
  760. case USB_REQ_SET_FEATURE:
  761. case USB_REQ_SET_INTERFACE:
  762. case USB_REQ_CLEAR_FEATURE:
  763. case USB_MSC_BBB_RESET:
  764. /* control transfer in status phase */
  765. if (ctrlreq_in_status_phase(dev) < 0)
  766. return 0;
  767. break;
  768. case USB_REQ_SET_DESCRIPTOR:
  769. /* control transfer out data phase */
  770. if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
  771. return 0;
  772. /* control transfer in status phase */
  773. if (ctrlreq_in_status_phase(dev) < 0)
  774. return 0;
  775. break;
  776. default:
  777. /* unhandled control transfer */
  778. return -1;
  779. }
  780. dev->status = 0;
  781. dev->act_len = len;
  782. return len;
  783. }
  784. /*
  785. * do a bulk transfer
  786. */
  787. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  788. void *buffer, int len)
  789. {
  790. int dir_out = usb_pipeout(pipe);
  791. int ep = usb_pipeendpoint(pipe);
  792. #ifndef MUSB_NO_MULTIPOINT
  793. int devnum = usb_pipedevice(pipe);
  794. #endif
  795. u8 type;
  796. u16 csr;
  797. u32 txlen = 0;
  798. u32 nextlen = 0;
  799. u8 devspeed;
  800. /* select bulk endpoint */
  801. writeb(MUSB_BULK_EP, &musbr->index);
  802. #ifndef MUSB_NO_MULTIPOINT
  803. /* write the address of the device */
  804. if (dir_out)
  805. writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
  806. else
  807. writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
  808. #endif
  809. /* configure the hub address and the port number as required */
  810. devspeed = get_dev_speed(dev);
  811. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  812. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  813. /*
  814. * MUSB is in high speed and the destination device is full
  815. * speed device. So configure the hub address and port
  816. * address registers.
  817. */
  818. config_hub_port(dev, MUSB_BULK_EP);
  819. } else {
  820. #ifndef MUSB_NO_MULTIPOINT
  821. if (dir_out) {
  822. writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
  823. writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
  824. } else {
  825. writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
  826. writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
  827. }
  828. #endif
  829. devspeed = musb_cfg.musb_speed;
  830. }
  831. /* Write the saved toggle bit value */
  832. write_toggle(dev, ep, dir_out);
  833. if (dir_out) { /* bulk-out transfer */
  834. /* Program the TxType register */
  835. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  836. (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
  837. (ep & MUSB_TYPE_REMOTE_END);
  838. writeb(type, &musbr->txtype);
  839. /* Write maximum packet size to the TxMaxp register */
  840. writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
  841. while (txlen < len) {
  842. nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
  843. (len-txlen) : dev->epmaxpacketout[ep];
  844. /* Write the data to the FIFO */
  845. write_fifo(MUSB_BULK_EP, nextlen,
  846. (void *)(((u8 *)buffer) + txlen));
  847. /* Set the TxPktRdy bit */
  848. csr = readw(&musbr->txcsr);
  849. writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
  850. /* Wait until the TxPktRdy bit is cleared */
  851. if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
  852. readw(&musbr->txcsr);
  853. usb_settoggle(dev, ep, dir_out,
  854. (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
  855. dev->act_len = txlen;
  856. return 0;
  857. }
  858. txlen += nextlen;
  859. }
  860. /* Keep a copy of the data toggle bit */
  861. csr = readw(&musbr->txcsr);
  862. usb_settoggle(dev, ep, dir_out,
  863. (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
  864. } else { /* bulk-in transfer */
  865. /* Write the saved toggle bit value */
  866. write_toggle(dev, ep, dir_out);
  867. /* Program the RxType register */
  868. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  869. (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
  870. (ep & MUSB_TYPE_REMOTE_END);
  871. writeb(type, &musbr->rxtype);
  872. /* Write the maximum packet size to the RxMaxp register */
  873. writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
  874. while (txlen < len) {
  875. nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
  876. (len-txlen) : dev->epmaxpacketin[ep];
  877. /* Set the ReqPkt bit */
  878. csr = readw(&musbr->rxcsr);
  879. writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
  880. /* Wait until the RxPktRdy bit is set */
  881. if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
  882. csr = readw(&musbr->rxcsr);
  883. usb_settoggle(dev, ep, dir_out,
  884. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  885. csr &= ~MUSB_RXCSR_RXPKTRDY;
  886. writew(csr, &musbr->rxcsr);
  887. dev->act_len = txlen;
  888. return 0;
  889. }
  890. /* Read the data from the FIFO */
  891. read_fifo(MUSB_BULK_EP, nextlen,
  892. (void *)(((u8 *)buffer) + txlen));
  893. /* Clear the RxPktRdy bit */
  894. csr = readw(&musbr->rxcsr);
  895. csr &= ~MUSB_RXCSR_RXPKTRDY;
  896. writew(csr, &musbr->rxcsr);
  897. txlen += nextlen;
  898. }
  899. /* Keep a copy of the data toggle bit */
  900. csr = readw(&musbr->rxcsr);
  901. usb_settoggle(dev, ep, dir_out,
  902. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  903. }
  904. /* bulk transfer is complete */
  905. dev->status = 0;
  906. dev->act_len = len;
  907. return 0;
  908. }
  909. /*
  910. * This function initializes the usb controller module.
  911. */
  912. int usb_lowlevel_init(void)
  913. {
  914. u8 power;
  915. u32 timeout;
  916. musb_rh_init();
  917. if (musb_platform_init() == -1)
  918. return -1;
  919. /* Configure all the endpoint FIFO's and start usb controller */
  920. musbr = musb_cfg.regs;
  921. musb_configure_ep(&epinfo[0],
  922. sizeof(epinfo) / sizeof(struct musb_epinfo));
  923. musb_start();
  924. /*
  925. * Wait until musb is enabled in host mode with a timeout. There
  926. * should be a usb device connected.
  927. */
  928. timeout = musb_cfg.timeout;
  929. while (timeout--)
  930. if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
  931. break;
  932. /* if musb core is not in host mode, then return */
  933. if (!timeout)
  934. return -1;
  935. /* start usb bus reset */
  936. power = readb(&musbr->power);
  937. writeb(power | MUSB_POWER_RESET, &musbr->power);
  938. /* After initiating a usb reset, wait for about 20ms to 30ms */
  939. udelay(30000);
  940. /* stop usb bus reset */
  941. power = readb(&musbr->power);
  942. power &= ~MUSB_POWER_RESET;
  943. writeb(power, &musbr->power);
  944. /* Determine if the connected device is a high/full/low speed device */
  945. musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
  946. MUSB_TYPE_SPEED_HIGH :
  947. ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
  948. MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
  949. return 0;
  950. }
  951. /*
  952. * This function stops the operation of the davinci usb module.
  953. */
  954. int usb_lowlevel_stop(void)
  955. {
  956. /* Reset the USB module */
  957. musb_platform_deinit();
  958. writeb(0, &musbr->devctl);
  959. return 0;
  960. }
  961. /*
  962. * This function supports usb interrupt transfers. Currently, usb interrupt
  963. * transfers are not supported.
  964. */
  965. int submit_int_msg(struct usb_device *dev, unsigned long pipe,
  966. void *buffer, int len, int interval)
  967. {
  968. int dir_out = usb_pipeout(pipe);
  969. int ep = usb_pipeendpoint(pipe);
  970. #ifndef MUSB_NO_MULTIPOINT
  971. int devnum = usb_pipedevice(pipe);
  972. #endif
  973. u8 type;
  974. u16 csr;
  975. u32 txlen = 0;
  976. u32 nextlen = 0;
  977. u8 devspeed;
  978. /* select interrupt endpoint */
  979. writeb(MUSB_INTR_EP, &musbr->index);
  980. #ifndef MUSB_NO_MULTIPOINT
  981. /* write the address of the device */
  982. if (dir_out)
  983. writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
  984. else
  985. writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
  986. #endif
  987. /* configure the hub address and the port number as required */
  988. devspeed = get_dev_speed(dev);
  989. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  990. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  991. /*
  992. * MUSB is in high speed and the destination device is full
  993. * speed device. So configure the hub address and port
  994. * address registers.
  995. */
  996. config_hub_port(dev, MUSB_INTR_EP);
  997. } else {
  998. #ifndef MUSB_NO_MULTIPOINT
  999. if (dir_out) {
  1000. writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
  1001. writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
  1002. } else {
  1003. writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
  1004. writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
  1005. }
  1006. #endif
  1007. devspeed = musb_cfg.musb_speed;
  1008. }
  1009. /* Write the saved toggle bit value */
  1010. write_toggle(dev, ep, dir_out);
  1011. if (!dir_out) { /* intrrupt-in transfer */
  1012. /* Write the saved toggle bit value */
  1013. write_toggle(dev, ep, dir_out);
  1014. writeb(interval, &musbr->rxinterval);
  1015. /* Program the RxType register */
  1016. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  1017. (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
  1018. (ep & MUSB_TYPE_REMOTE_END);
  1019. writeb(type, &musbr->rxtype);
  1020. /* Write the maximum packet size to the RxMaxp register */
  1021. writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
  1022. while (txlen < len) {
  1023. nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
  1024. (len-txlen) : dev->epmaxpacketin[ep];
  1025. /* Set the ReqPkt bit */
  1026. csr = readw(&musbr->rxcsr);
  1027. writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
  1028. /* Wait until the RxPktRdy bit is set */
  1029. if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
  1030. csr = readw(&musbr->rxcsr);
  1031. usb_settoggle(dev, ep, dir_out,
  1032. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  1033. csr &= ~MUSB_RXCSR_RXPKTRDY;
  1034. writew(csr, &musbr->rxcsr);
  1035. dev->act_len = txlen;
  1036. return 0;
  1037. }
  1038. /* Read the data from the FIFO */
  1039. read_fifo(MUSB_INTR_EP, nextlen,
  1040. (void *)(((u8 *)buffer) + txlen));
  1041. /* Clear the RxPktRdy bit */
  1042. csr = readw(&musbr->rxcsr);
  1043. csr &= ~MUSB_RXCSR_RXPKTRDY;
  1044. writew(csr, &musbr->rxcsr);
  1045. txlen += nextlen;
  1046. }
  1047. /* Keep a copy of the data toggle bit */
  1048. csr = readw(&musbr->rxcsr);
  1049. usb_settoggle(dev, ep, dir_out,
  1050. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  1051. }
  1052. /* interrupt transfer is complete */
  1053. dev->irq_status = 0;
  1054. dev->irq_act_len = len;
  1055. dev->irq_handle(dev);
  1056. dev->status = 0;
  1057. dev->act_len = len;
  1058. return 0;
  1059. }
  1060. #ifdef CONFIG_SYS_USB_EVENT_POLL
  1061. /*
  1062. * This function polls for USB keyboard data.
  1063. */
  1064. void usb_event_poll()
  1065. {
  1066. struct stdio_dev *dev;
  1067. struct usb_device *usb_kbd_dev;
  1068. struct usb_interface *iface;
  1069. struct usb_endpoint_descriptor *ep;
  1070. int pipe;
  1071. int maxp;
  1072. /* Get the pointer to USB Keyboard device pointer */
  1073. dev = stdio_get_by_name("usbkbd");
  1074. usb_kbd_dev = (struct usb_device *)dev->priv;
  1075. iface = &usb_kbd_dev->config.if_desc[0];
  1076. ep = &iface->ep_desc[0];
  1077. pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
  1078. /* Submit a interrupt transfer request */
  1079. maxp = usb_maxpacket(usb_kbd_dev, pipe);
  1080. usb_submit_int_msg(usb_kbd_dev, pipe, &new[0],
  1081. maxp > 8 ? 8 : maxp, ep->bInterval);
  1082. }
  1083. #endif /* CONFIG_SYS_USB_EVENT_POLL */