mx6qsabrelite.c 13 KB

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  1. /*
  2. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/imx-regs.h>
  25. #include <asm/arch/mx6x_pins.h>
  26. #include <asm/arch/iomux-v3.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/errno.h>
  29. #include <asm/gpio.h>
  30. #include <mmc.h>
  31. #include <fsl_esdhc.h>
  32. #include <micrel.h>
  33. #include <miiphy.h>
  34. #include <netdev.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  37. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  38. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  40. PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  41. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  43. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  45. #define SPI_PAD_CTRL (PAD_CTL_HYS | \
  46. PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
  47. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  48. #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  49. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  50. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  52. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  53. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  54. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55. int dram_init(void)
  56. {
  57. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  58. return 0;
  59. }
  60. iomux_v3_cfg_t uart1_pads[] = {
  61. MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  62. MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. };
  64. iomux_v3_cfg_t uart2_pads[] = {
  65. MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  66. MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  67. };
  68. iomux_v3_cfg_t i2c3_pads[] = {
  69. MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  70. MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  71. };
  72. iomux_v3_cfg_t usdhc3_pads[] = {
  73. MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74. MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75. MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76. MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  80. };
  81. iomux_v3_cfg_t usdhc4_pads[] = {
  82. MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83. MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84. MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85. MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86. MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87. MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88. MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  89. };
  90. iomux_v3_cfg_t enet_pads1[] = {
  91. MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93. MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94. MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95. MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96. MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97. MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98. MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99. MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  100. /* pin 35 - 1 (PHY_AD2) on reset */
  101. MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. /* pin 32 - 1 - (MODE0) all */
  103. MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  104. /* pin 31 - 1 - (MODE1) all */
  105. MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  106. /* pin 28 - 1 - (MODE2) all */
  107. MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  108. /* pin 27 - 1 - (MODE3) all */
  109. MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  110. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  111. MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  112. /* pin 42 PHY nRST */
  113. MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  114. };
  115. iomux_v3_cfg_t enet_pads2[] = {
  116. MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  117. MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  118. MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  119. MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  120. MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  121. MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  122. };
  123. /* Button assignments for J14 */
  124. static iomux_v3_cfg_t button_pads[] = {
  125. /* Menu */
  126. MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  127. /* Back */
  128. MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  129. /* Labelled Search (mapped to Power under Android) */
  130. MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  131. /* Home */
  132. MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  133. /* Volume Down */
  134. MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  135. /* Volume Up */
  136. MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  137. };
  138. static void setup_iomux_enet(void)
  139. {
  140. gpio_direction_output(87, 0); /* GPIO 3-23 */
  141. gpio_direction_output(190, 1); /* GPIO 6-30 */
  142. gpio_direction_output(185, 1); /* GPIO 6-25 */
  143. gpio_direction_output(187, 1); /* GPIO 6-27 */
  144. gpio_direction_output(188, 1); /* GPIO 6-28*/
  145. gpio_direction_output(189, 1); /* GPIO 6-29 */
  146. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  147. gpio_direction_output(184, 1); /* GPIO 6-24 */
  148. /* Need delay 10ms according to KSZ9021 spec */
  149. udelay(1000 * 10);
  150. gpio_set_value(87, 1); /* GPIO 3-23 */
  151. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  152. }
  153. iomux_v3_cfg_t usb_pads[] = {
  154. MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  155. };
  156. static void setup_iomux_uart(void)
  157. {
  158. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  159. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  160. }
  161. #ifdef CONFIG_USB_EHCI_MX6
  162. int board_ehci_hcd_init(int port)
  163. {
  164. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  165. /* Reset USB hub */
  166. gpio_direction_output(GPIO_NUMBER(7, 12), 0);
  167. mdelay(2);
  168. gpio_set_value(GPIO_NUMBER(7, 12), 1);
  169. return 0;
  170. }
  171. #endif
  172. #ifdef CONFIG_FSL_ESDHC
  173. struct fsl_esdhc_cfg usdhc_cfg[2] = {
  174. {USDHC3_BASE_ADDR, 1},
  175. {USDHC4_BASE_ADDR, 1},
  176. };
  177. int board_mmc_getcd(struct mmc *mmc)
  178. {
  179. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  180. int ret;
  181. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  182. gpio_direction_input(192); /*GPIO7_0*/
  183. ret = !gpio_get_value(192);
  184. } else {
  185. gpio_direction_input(38); /*GPIO2_6*/
  186. ret = !gpio_get_value(38);
  187. }
  188. return ret;
  189. }
  190. int board_mmc_init(bd_t *bis)
  191. {
  192. s32 status = 0;
  193. u32 index = 0;
  194. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  195. switch (index) {
  196. case 0:
  197. imx_iomux_v3_setup_multiple_pads(
  198. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  199. break;
  200. case 1:
  201. imx_iomux_v3_setup_multiple_pads(
  202. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  203. break;
  204. default:
  205. printf("Warning: you configured more USDHC controllers"
  206. "(%d) then supported by the board (%d)\n",
  207. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  208. return status;
  209. }
  210. status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  211. }
  212. return status;
  213. }
  214. #endif
  215. u32 get_board_rev(void)
  216. {
  217. return 0x63000 ;
  218. }
  219. #ifdef CONFIG_MXC_SPI
  220. iomux_v3_cfg_t ecspi1_pads[] = {
  221. /* SS1 */
  222. MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  223. MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  224. MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  225. MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  226. };
  227. void setup_spi(void)
  228. {
  229. gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
  230. imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  231. ARRAY_SIZE(ecspi1_pads));
  232. }
  233. #endif
  234. int board_phy_config(struct phy_device *phydev)
  235. {
  236. /* min rx data delay */
  237. ksz9021_phy_extended_write(phydev,
  238. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  239. /* min tx data delay */
  240. ksz9021_phy_extended_write(phydev,
  241. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  242. /* max rx/tx clock delay, min rx/tx control */
  243. ksz9021_phy_extended_write(phydev,
  244. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  245. if (phydev->drv->config)
  246. phydev->drv->config(phydev);
  247. return 0;
  248. }
  249. int board_eth_init(bd_t *bis)
  250. {
  251. int ret;
  252. setup_iomux_enet();
  253. ret = cpu_eth_init(bis);
  254. if (ret)
  255. printf("FEC MXC: %s:failed\n", __func__);
  256. return 0;
  257. }
  258. static void setup_buttons(void)
  259. {
  260. imx_iomux_v3_setup_multiple_pads(button_pads,
  261. ARRAY_SIZE(button_pads));
  262. }
  263. #ifdef CONFIG_CMD_SATA
  264. int setup_sata(void)
  265. {
  266. struct iomuxc_base_regs *const iomuxc_regs
  267. = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
  268. int ret = enable_sata_clock();
  269. if (ret)
  270. return ret;
  271. clrsetbits_le32(&iomuxc_regs->gpr[13],
  272. IOMUXC_GPR13_SATA_MASK,
  273. IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
  274. |IOMUXC_GPR13_SATA_PHY_7_SATA2M
  275. |IOMUXC_GPR13_SATA_SPEED_3G
  276. |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
  277. |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
  278. |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
  279. |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
  280. |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
  281. |IOMUXC_GPR13_SATA_PHY_1_SLOW);
  282. return 0;
  283. }
  284. #endif
  285. int board_early_init_f(void)
  286. {
  287. setup_iomux_uart();
  288. setup_buttons();
  289. return 0;
  290. }
  291. int board_init(void)
  292. {
  293. /* address of boot parameters */
  294. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  295. #ifdef CONFIG_MXC_SPI
  296. setup_spi();
  297. #endif
  298. imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
  299. #ifdef CONFIG_CMD_SATA
  300. setup_sata();
  301. #endif
  302. return 0;
  303. }
  304. int checkboard(void)
  305. {
  306. puts("Board: MX6Q-Sabre Lite\n");
  307. return 0;
  308. }
  309. struct button_key {
  310. char const *name;
  311. unsigned gpnum;
  312. char ident;
  313. };
  314. static struct button_key const buttons[] = {
  315. {"back", GPIO_NUMBER(2, 2), 'B'},
  316. {"home", GPIO_NUMBER(2, 4), 'H'},
  317. {"menu", GPIO_NUMBER(2, 1), 'M'},
  318. {"search", GPIO_NUMBER(2, 3), 'S'},
  319. {"volup", GPIO_NUMBER(7, 13), 'V'},
  320. {"voldown", GPIO_NUMBER(4, 5), 'v'},
  321. };
  322. /*
  323. * generate a null-terminated string containing the buttons pressed
  324. * returns number of keys pressed
  325. */
  326. static int read_keys(char *buf)
  327. {
  328. int i, numpressed = 0;
  329. for (i = 0; i < ARRAY_SIZE(buttons); i++) {
  330. if (!gpio_get_value(buttons[i].gpnum))
  331. buf[numpressed++] = buttons[i].ident;
  332. }
  333. buf[numpressed] = '\0';
  334. return numpressed;
  335. }
  336. static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  337. {
  338. char envvalue[ARRAY_SIZE(buttons)+1];
  339. int numpressed = read_keys(envvalue);
  340. setenv("keybd", envvalue);
  341. return numpressed == 0;
  342. }
  343. U_BOOT_CMD(
  344. kbd, 1, 1, do_kbd,
  345. "Tests for keypresses, sets 'keybd' environment variable",
  346. "Returns 0 (true) to shell if key is pressed."
  347. );
  348. #ifdef CONFIG_PREBOOT
  349. static char const kbd_magic_prefix[] = "key_magic";
  350. static char const kbd_command_prefix[] = "key_cmd";
  351. static void preboot_keys(void)
  352. {
  353. int numpressed;
  354. char keypress[ARRAY_SIZE(buttons)+1];
  355. numpressed = read_keys(keypress);
  356. if (numpressed) {
  357. char *kbd_magic_keys = getenv("magic_keys");
  358. char *suffix;
  359. /*
  360. * loop over all magic keys
  361. */
  362. for (suffix = kbd_magic_keys; *suffix; ++suffix) {
  363. char *keys;
  364. char magic[sizeof(kbd_magic_prefix) + 1];
  365. sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
  366. keys = getenv(magic);
  367. if (keys) {
  368. if (!strcmp(keys, keypress))
  369. break;
  370. }
  371. }
  372. if (*suffix) {
  373. char cmd_name[sizeof(kbd_command_prefix) + 1];
  374. char *cmd;
  375. sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
  376. cmd = getenv(cmd_name);
  377. if (cmd) {
  378. setenv("preboot", cmd);
  379. return;
  380. }
  381. }
  382. }
  383. }
  384. #endif
  385. int misc_init_r(void)
  386. {
  387. #ifdef CONFIG_PREBOOT
  388. preboot_keys();
  389. #endif
  390. return 0;
  391. }